Gate Driving Circuit Signal Delay Adjustment for Display Luminance
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Solution Overview
Problem
In liquid crystal display apparatuses, luminance deviations occur due to unsynchronized gate or data signals, leading to suboptimal image quality.
Innovation Solution
The display apparatus incorporates a gate driving part and a data driving part that adjust signal delays based on the increasing or decreasing load of the gate lines, ensuring synchronized signal output to the gate and data lines, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate signals are transmitted without delay adjustment, then the device complexity is reduced, but luminance deviation occurs due to unsynchronized signals
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-setting different delay times for gate signals before they are transmitted to various gate lines. The gate driving circuit incorporates delay adjustment functionality that compensates for load differences in advance, ensuring that signals arrive at all gate lines simultaneously despite varying line characteristics. This preliminary delay adjustment prevents luminance deviation without requiring complex real-time synchronization mechanisms.
2Manufacturing precision
If uniform delay is applied to all gate lines, then the device complexity is reduced, but luminance deviation occurs due to varying gate line loads
Solution Approach 1:
The patent implements local quality by applying different delay times to different gate lines based on their specific load characteristics. Rather than using a uniform delay for all lines, the gate driving circuit is designed to provide localized delay adjustment tailored to each gate line's capacitance and length. This ensures that signals compensate for their specific path characteristics, achieving uniform luminance across the display while maintaining reasonable circuit complexity through targeted rather than universal adjustment.
Data Source
AI summary
A display apparatus includes a display panel, a data driving part and a gate driving part. The display panel includes data lines extending in a first direction and arranged in a second direction substantially perpendicular to the first direction, and gate lines including a portion extending in the first direction and a portion extending in the second direction. The data driving part is configured to output data signals to the data lines to drive the data lines. The gate driving part is configured to delay original gate signals according to a decrease of a load of the gate line, and output gate signals generated by the delay of the original gate signals to the gate lines to drive the gate lines.


