Gate Driving Unit Pull-Up Node Control for LCD Leakage

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Solution Overview

Problem

Conventional gate driving circuits in liquid crystal displays face challenges with reduced transistor charging time and increased leakage current during the pull-up holding phase, limiting the driving capability and display quality, especially for large-sized high-resolution LCDs.

Innovation Solution

The proposed solution involves an array substrate gate driving unit with an input circuit, pull-down circuit, reset circuit, output circuit, and control circuit, including a control switching element and inverter, which controls the potential of the pull-up node and disconnects the control circuit to enhance the clock signal coupling effect, increase the turning-on voltage, and reduce leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the GOA circuit is used to integrate gate driving circuits on array substrate, then the manufacturing process is simplified and product costs are reduced, but the transistor charging time is significantly reduced for large-sized high-resolution LCD products

Engineering Contradiction:
Improvemanufacturing process simplificationVSAvoidtransistor charging time
Core Design Contradiction:
Ease of manufactureVSDuration of action of moving object

Solution Approach 1:

The patent changes the voltage parameter of the pull-up node by introducing a control circuit that can increase the voltage level during the pull-up holding phase. This voltage parameter change directly extends the charging time available for transistor gate capacitance, resolving the charging time limitation while maintaining the GOA integration structure

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces a dynamic control mechanism where the control circuit actively adjusts the pull-up node voltage based on operational phase. The circuit transitions from a static voltage level to a dynamic adjustable voltage level, enabling extended charging time during specific phases without affecting other operational characteristics

Inventive Principle:
Principle #15Dynamics

2Adaptability or versatility

If the existing GOA circuit structure is used, then the circuit integration is achieved, but the leakage current increases during the pull-up holding phase due to loads of input circuit, reset circuit, and pull-down circuit

Engineering Contradiction:
Improvecircuit integrationVSAvoidleakage current
Core Design Contradiction:
Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The control circuit extracts and isolates the pull-up holding function from the other circuit loads. By separating the pull-up node control from the input, reset, and pull-down circuits, the patent eliminates the leakage current contribution from these circuits during the holding phase, reducing total leakage while preserving circuit integration

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The control circuit acts as an intermediary between the pull-up node and the other circuits (input, reset, pull-down). It mediates the connection by controlling when these circuits are connected to the pull-up node, preventing their leakage currents from affecting the pull-up holding phase

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS10902810B2Array substrate gate driving unit and apparatus thereof, driving method and display apparatus
Publication Date: 2021.01.26 BOE TECHNOLOGY GROUP CO LTD
  • US10902810B2 patent drawing
  • US10902810B2 patent drawing
  • US10902810B2 patent drawing

AI summary

The present disclosure relates to an array substrate gate driving unit and an apparatus thereof, a driving method and a display apparatus. The array substrate gate driving unit includes: an input circuit, connected with an input signal terminal and a pull-up node PU; a pull-down circuit, connected with a first voltage signal terminal and the pull-up node PU; a pull-down control circuit, connected with the pull-down circuit via a pull-down node PD; an output circuit, connected with a clock signal terminal CLK, a second voltage signal terminal and a control circuit; a reset circuit, connected with a reset signal terminal Reset, the first voltage signal terminal and the pull-up node PU; and the control circuit, connected with the pull-up node PU and the output circuit.