Gate Driving Unit for Simultaneous Normal and Reverse Phase Signals
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Solution Overview
Problem
Conventional gate driving circuits struggle to simultaneously provide normal-phase and reverse-phase gate driving signals, which limits the charging and discharging rates of pixels in display devices, particularly in Low Temperature Polycrystalline Oxide (LTPO) pixel circuits, leading to suboptimal display quality and increased power consumption.
Innovation Solution
A gate driving unit comprising a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry, and an output circuitry, which uses NOR gates, phase inverters, and switching circuits to control the potential at the output node and enable simultaneous output of both signal phases, thereby enhancing the charging and discharging rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional gate driving circuitry is used, then the circuit structure is simple, but it cannot simultaneously provide normal-phase and reverse-phase gate driving signals, limiting charging/discharging rate
Solution Approach 1:
The gate driving circuit is divided into multiple functional modules: input circuitry, output control circuitry, input node control circuitry, and output circuitry. Each module performs a specific function in the signal generation and control process, enabling simultaneous output of normal-phase and reverse-phase signals through structured segmentation
Solution Approach 2:
An output node is introduced as an intermediary element that receives control signals from the input node control circuitry and the output control circuitry, and then drives the output circuitry to generate the final gate driving signals. This intermediary facilitates coordinated control of both signal phases
2Loss of energy
If refresh rate is reduced to lower power consumption, then energy efficiency improves, but display quality deteriorates due to voltage variation from current leakage
Solution Approach 1:
The circuit employs oxide TFTs with ultra-low current leakage properties to fundamentally change the electrical parameters of the pixel circuitry. This parameter change enables the system to maintain stable voltage levels even at lower refresh rates, thus reducing power consumption without compromising display quality
Solution Approach 2:
The patent combines LTPS TFTs and oxide TFTs in a hybrid architecture, leveraging the high charging rate advantage of LTPS and the ultra-low leakage advantage of oxide. This composite approach optimizes both power consumption and display quality by assigning different transistor types to different functional requirements
3Loss of energy
If oxide TFTs are used to reduce current leakage, then power consumption decreases, but charging rate may be insufficient compared to LTPS TFTs
Solution Approach 1:
Different transistor types are strategically assigned to different locations and functions within the pixel circuitry. Oxide TFTs are used where low leakage is critical (e.g., switching transistors), while LTPS TFTs are used where high charging rate is needed (e.g., driving transistors). This local optimization resolves the contradiction between leakage reduction and charging speed
Data Source
AI summary
The present disclosure provides a gate driving unit, a gate driving method, a gate driving circuitry and a display device. The gate driving unit includes a reverse-phase gate driving signal output end, a normal-phase gate driving signal output end, an input circuitry, an output control circuitry, an input node control circuitry and an output circuitry. The input circuitry is configured to control an input end to be electrically connected to an input node under the control of a first clock signal. The output control circuitry is configured to control a potential at an output node under the control of a potential at the input node and a second clock signal. The input node control circuitry is configured to control the potential at the input node in accordance with the potential at the output node under the control of the second clock signal. The output circuitry is configured to output a reverse-phase gate driving signal and output a normal-phase gate driving signal in accordance with the potential at the output node.