Gate Insulating Layers With Dual Dipoles for Threshold Voltage Control
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Solution Overview
Problem
It is challenging to lower the threshold voltage of NMOS and PMOS transistors and control the thickness of the inversion area as the integration degree of semiconductor devices increases.
Innovation Solution
The use of different dipole materials in the gate insulating layers of NMOS and PMOS transistors, such as N-type and P-type dipole materials in silicon oxide layers, to form specific gate stacks that allow for the diffusion of these materials during annealing processes, thereby adjusting the threshold voltage and inversion region thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the integration degree of semiconductor devices is increased, then device density and miniaturization are improved, but it becomes difficult to lower the threshold voltage of NMOS and PMOS transistors and control the thickness of the inversion area
Solution Approach 1:
The patent applies local quality by introducing different dipole materials (first dipole material for NMOS, second dipole material for PMOS) into the gate insulating layers at different locations. This allows each transistor type to have locally optimized electrical characteristics, enabling threshold voltage control and inversion area thickness management despite high integration density.
Solution Approach 2:
The patent utilizes parameter changes by varying the dipole material composition and concentration in the gate insulating layers. By adjusting the types and amounts of dipole materials, the electrical parameters (threshold voltage, inversion area thickness) can be precisely controlled while maintaining high device integration.
2Ease of manufacture
If conventional gate insulating layers are used in high integration devices, then manufacturing simplicity is maintained, but threshold voltage cannot be effectively lowered and inversion area thickness cannot be controlled
Solution Approach 1:
The patent employs composite materials by combining silicon oxide with different dipole materials to create gate insulating layers with tailored properties. The first gate insulating layer contains silicon oxide and a first dipole material, while the second gate insulating layer contains silicon oxide and a second dipole material, achieving both manufacturability and precise electrical control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers the threshold voltage and improves the thickness of the inversion region for both NMOS and PMOS transistors, enhancing their performance.
Implementation Method 1
performing a first annealing process to diffuse the first dipole material in the first dipole material layer and silicon atoms in the silicon source layer into the first preliminary lower gate insulating layer
Data Source
AI summary
A semiconductor device includes a first gate stack and a second gate stack disposed on a substrate. The first gate stack includes a first lower gate insulating layer. The second gate stack includes a second lower gate insulating layer. The first lower gate insulating layer includes silicon oxide with a first dipole material. The second lower gate insulating layer includes silicon oxide with a second dipole material. The first dipole material and the second dipole material are different from each other.