Gate Structure With Dual High-k Dielectric Layers For Threshold Voltage Tuning
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Solution Overview
Problem
Conventional semiconductor devices face challenges in tuning threshold voltages as device scaling down leads to increased gate resistance and manufacturing difficulties, particularly in advanced technology nodes where gate fill window for multiple threshold voltage tuning becomes difficult due to gate length dimension shrinkage.
Innovation Solution
The proposed solution involves improving the gate fill window and reducing gate resistance by selectively driving specific metal or boron ions into a first high-k dielectric layer of the gate structure at various concentrations to tune threshold voltages, and including a second high-k dielectric layer to reduce gate leakage, along with work function barrier layers of different thicknesses to enhance threshold voltage tuning flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scaling down is implemented to increase functional density, then production efficiency is improved and costs are lowered, but gate resistance increases and manufacturing complexity increases
Solution Approach 1:
The patent changes the physical and chemical parameters of the gate structure by introducing high-k dielectric materials with different dielectric constants, adjusting layer thicknesses, and modifying doping concentrations to reduce gate resistance while maintaining scaled dimensions
Solution Approach 2:
The patent uses composite gate structures combining multiple materials (high-k dielectric layers, metal gates, doped regions) to achieve optimized electrical properties that single materials cannot provide, specifically reducing gate resistance in scaled devices
2Productivity
If gate length dimension is shrunk to increase functional density, then production efficiency is improved, but gate fill window for threshold voltage tuning becomes difficult
Solution Approach 1:
The patent transitions from single-layer to multi-layer gate structures, adding vertical dimensionality with multiple high-k dielectric layers of different thicknesses to provide additional tuning degrees of freedom for threshold voltage control
Solution Approach 2:
The gate dielectric structure is segmented into multiple layers with different properties (first high-k dielectric layer, second high-k dielectric layer with different thickness), allowing independent optimization of each layer for threshold voltage tuning
3Ease of manufacture
If conventional gate structures are used in advanced technology nodes, then manufacturing process is simple, but gate leakage increases
Solution Approach 1:
The patent employs composite gate dielectric structures combining high-k dielectric materials with different properties to reduce gate leakage while maintaining manufacturability through established deposition and processing techniques
Solution Approach 2:
The patent modifies dielectric constant parameters and layer thickness parameters to optimize the balance between gate leakage reduction and manufacturing simplicity in advanced technology nodes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for flexible tuning of threshold voltages with improved gate fill window and reduced gate resistance, enabling efficient fabrication of semiconductor devices with multiple threshold voltages without significant modification to the fabrication process.
Implementation Method 1
selectively driving specific metal or boron ions into a first high-k dielectric layer of the gate structure at various concentrations to tune threshold voltages
Implementation Method 2
including a second high-k dielectric layer to reduce gate leakage
Data Source
AI summary
A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.