Gate Electrode Formation via Asymmetric Dummy Gate Etching
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Solution Overview
Problem
As semiconductor device dimensions decrease, filling conductive material into increasingly smaller openings becomes difficult, affecting the quality and performance of gate structures in high-k metal gate (HKMG) semiconductor devices due to higher aspect ratios of the openings.
Innovation Solution
A method is introduced to fabricate semiconductor structures by forming dummy gate structures with sidewall spacers, removing portions of the dummy gate electrodes and spacers to create openings with larger dimensions at the top than at the bottom, facilitating easier filling of conductive material and improving gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the critical dimensions of semiconductor devices are continuously decreased to improve integration degree, then the integration degree is improved, but the aspect ratio of openings increases making filling more difficult
Solution Approach 1:
The patent applies asymmetry by creating openings with non-uniform cross-sections where the width varies along the depth. Specifically, the openings have larger openings at the top and smaller openings at the bottom, or vice versa, depending on the fabrication stage. This asymmetric geometry reduces the aspect ratio effect by providing larger access areas for material deposition while maintaining the required small dimensions at the critical interface, thereby facilitating filling operations in high-aspect-ratio structures
Solution Approach 2:
The patent addresses the filling difficulty by transitioning from a one-dimensional depth problem to a two-dimensional cross-sectional problem. By varying the opening width in the lateral dimension while maintaining the vertical depth, the effective aspect ratio is reduced. The method creates openings that are wider at certain depths to allow better material access and distribution, effectively solving the filling problem by adding dimensional complexity to the opening geometry
2Speed
If the size of gate electrode is decreased to reduce parasitic capacitance, then the operation speed is improved, but the quality of gate structure is degraded due to filling difficulties
Solution Approach 1:
The patent uses asymmetric opening geometries to maintain small gate electrode dimensions for low parasitic capacitance while ensuring adequate material filling. The openings are designed with varying widths that provide larger access areas for conductive material deposition, allowing precise control of the gate electrode formation process even at reduced dimensions, thereby maintaining manufacturing precision
Solution Approach 2:
The patent employs preliminary actions by forming dummy gate structures and sidewall spacers before creating the final openings. These preliminary structures serve as templates and masks that define the precise geometry of the openings, ensuring that when the openings are formed and filled, the resulting gate electrodes have the exact dimensions and quality required for high-speed operation
Data Source
AI summary
A method for fabricating a semiconductor structure includes forming a plurality of dummy gate structures on a substrate. Each dummy gate structure includes a gate dielectric layer, a dummy gate electrode, and two sidewall spacers. The method also includes forming a dielectric layer on the substrate between neighboring dummy gate structures and removing a portion of each dummy gate electrode to form a first opening. The first opening is surrounded by a remaining portion of the dummy gate electrode and the two sidewall spacers. The method further includes removing a portion of each sidewall spacer along a direction perpendicular to the sidewall of the first opening to form a second opening, removing the remaining portion of the gate electrode on the bottom of each second opening to form a third opening, and then filling each third opening with a gate electrode material to form a gate electrode.