Gate Electrode Bridging Prevention in FinFET Manufacturing
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Solution Overview
Problem
As semiconductor device size shrinks and density increases, there is a risk of short circuits and defects due to residual conductive material bridging adjacent gate electrodes during etching operations, necessitating a process to eliminate bridging across adjacent gate electrodes.
Innovation Solution
The process involves forming insulating layers between adjacent gate electrodes, including an oxidation or nitridation treatment and depositing insulating materials to ensure electrical separation, followed by the formation of high-k gate dielectric and metal gate electrode layers, which are electrically separated by these insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device size is shrunk and density is increased, then device integration and functionality are improved, but the risk of short circuits and defects due to residual conductive material bridging adjacent gate electrodes increases
Solution Approach 1:
The patent extracts and removes residual conductive material from between adjacent gate electrodes through selective etching processes. The method involves forming a sacrificial layer between gate electrodes, etching the gate electrodes, and then removing the sacrificial layer to eliminate bridging risks, thereby maintaining high density while preventing short circuits
Solution Approach 2:
The patent introduces a sacrificial layer as an intermediary material between adjacent gate electrodes during the manufacturing process. This sacrificial layer prevents direct contact and potential bridging of conductive material between gate electrodes, and is subsequently removed to eliminate the intermediary while ensuring no residual bridging remains
2Ease of manufacture
If conventional etching operations are used to cut gate electrodes, then manufacturing simplicity is maintained, but residual conductive material bridges adjacent gate electrodes causing short circuits
Solution Approach 1:
The patent performs preliminary actions by forming a sacrificial layer between gate electrodes before the etching operation. This preliminary structure enables precise control of the etching process and ensures that residual conductive material does not bridge adjacent gate electrodes, achieving both manufacturing feasibility and defect prevention
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: forming the sacrificial layer, etching the gate electrodes with controlled separation, and removing the sacrificial layer. This segmentation allows each step to be optimized independently, maintaining ease of manufacture while achieving precise bridging prevention
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the number of defects and increases device yield by preventing electrical bridging between gate electrodes, leading to improved manufacturing efficiency and higher semiconductor device reliability.
Implementation Method 1
An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers
Implementation Method 2
An oxidation or nitridation treatment is performed in a region between the two spaced apart gate electrode layers
Data Source
AI summary
A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.