Gate Electrode Layering for Scaled MOSFET Channel Reliability
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Solution Overview
Problem
The scale-down of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices leads to deterioration in operational properties, necessitating improved electric characteristics.
Innovation Solution
A semiconductor device design featuring a gate electrode with distinct electrode portions and an etch barrier pattern, including a first metal pattern, etch barrier pattern, and second metal pattern, which are sequentially layered and thinner than the first metal pattern, to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOS-FETs are scaled down to meet increasing demand for smaller pattern sizes, then device size is reduced, but operational properties deteriorate
Solution Approach 1:
The gate electrode is divided into first and second electrode portions with different structures. The first electrode portion has a single metal pattern while the second electrode portion has multiple stacked metal patterns (first metal pattern, etch barrier pattern, second metal pattern). This segmentation allows each portion to be optimized for its specific functional requirements, improving overall device performance while maintaining small size.
Solution Approach 2:
Different regions of the gate electrode are given different local structures and materials. The second electrode portion uses a multi-layer structure with specific thickness ratios (etch barrier pattern thinner than first and second metal patterns) to provide localized stress management and electrical optimization, while the first electrode portion uses a simpler structure. This local differentiation resolves the contradiction by allowing size reduction without uniform performance degradation.
2Device complexity
If the etch barrier pattern is made thinner to reduce complexity, then manufacturing is simplified, but stress management and stacking fault prevention are compromised
Solution Approach 1:
The thickness of the etch barrier pattern is precisely controlled to be thinner than both the first metal pattern and the second metal pattern in the second electrode portion. This parameter optimization maintains sufficient stress management capability and stacking fault prevention while reducing overall gate electrode complexity and improving manufacturability.
Solution Approach 2:
The gate electrode uses composite material structures with an etch barrier pattern positioned between first and second metal patterns. This composite structure provides both mechanical support for stress management and etching selectivity, achieving reliable stacking fault prevention with controlled complexity through material composition rather than sheer thickness.
Data Source
AI summary
A semiconductor device may include a substrate including first and second active regions, which are adjacent to each other, first and second active patterns provided on the first and second active regions, respectively, and a gate electrode extended to cross the first and second active patterns. The gate electrode may include first and second electrode portions provided on the first and second active regions, respectively. The second electrode portion may include a first metal pattern, an etch barrier pattern, a second metal pattern, and a third metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etch barrier pattern may be in contact with the first metal pattern and the second metal pattern, and the etch barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern.