Gate Electrode Concave Structure for Parasitic Transistor Suppression
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Solution Overview
Problem
Semiconductor devices with shallow trench isolation (STI) structures face issues with parasitic transistors forming at the end portions of the element region, leading to hump properties that deviate from the original MOS transistor properties and reduce circuit operating margins, and existing solutions that branch off the gate electrode at the end portion result in a smaller channel width and increased element area to compensate for current driving force.
Innovation Solution
A semiconductor device and manufacturing method involving a gate electrode with concave and protruding portions at its ends, where ion implantation of impurities is performed through the concave portions to form impurity regions that contact the element isolation region, while maintaining a continuous gate electrode, thus suppressing parasitic transistors and preventing an increase in element area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode is branched off at the end portion of the element region to prevent parasitic transistor formation, then hump properties are improved, but the channel width becomes smaller and current driving force is reduced
Solution Approach 1:
The gate electrode is designed with different structures at different locations: the main body maintains full width for current driving, while the end portions feature concave portions that create local gaps to suppress parasitic transistors. This local differentiation resolves the contradiction by applying the parasitic suppression structure only where needed rather than reducing the overall channel width.
Solution Approach 2:
The gate electrode is segmented into a main body portion and end portions with concave portions. The concave portions create separate regions that prevent continuous parasitic transistor formation while maintaining the overall gate structure. This segmentation allows the channel to maintain sufficient width for current driving while preventing parasitic effects at critical end regions.
2Reliability
If the gate electrode is branched off at the end portion of the element region to prevent parasitic transistor formation, then hump properties are improved, but the element area must increase to obtain predetermined current driving force
Solution Approach 1:
Instead of increasing overall element area, the solution applies localized concave portions only at the end portions of the gate electrode where parasitic transistors form. This maintains the full channel width and element area in the main region while suppressing parasitic effects locally at the ends.
3Reliability
If ion implantation is performed through the concave portions of the gate electrode, then impurity regions are formed that suppress parasitic transistors, but the manufacturing process becomes more complex
Solution Approach 1:
The concave portions are formed in the gate electrode before the ion implantation step. This preliminary structuring creates self-aligned regions that guide the ion implantation process, ensuring impurity regions are formed precisely where needed to suppress parasitic transistors without requiring additional alignment steps or complex masking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves hump properties while restraining the increase in element area, maintaining a sufficient current driving force and preventing reduction in resistance voltage, suitable for high-voltage resistant MOS transistors.
Implementation Method 1
both end portions of the gate electrode in the first direction being on the element isolation region and each including a concave portion and protruding portions at both sides of the concave portion
Implementation Method 2
carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are respectively formed
Data Source
AI summary
Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.