Multilayer Gate Electrode Copper Diffusion Barrier

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Solution Overview

Problem

The formation of a planarizing film using SOG material on active matrix substrates leads to oxidation of copper films and diffusion of copper into the SOG material, resulting in increased resistance and dielectric constant, which deteriorates insulation performance.

Innovation Solution

A multilayer gate electrode structure is used, where the first and third conductive films are made of metals other than copper, such as titanium or tungsten, to prevent copper oxidation and diffusion during the dehydration polymerization of the SOG material, while allowing copper to be used in the second conductive film for low resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Shape

If a planarizing film is formed by baking SOG material at high temperature, then the surface is planarized, but copper oxidation and diffusion occur causing increased resistance and deteriorated insulation performance

Engineering Contradiction:
Improvesurface planarityVSAvoidinsulation performance
Core Design Contradiction:
ShapeVSReliability

Solution Approach 1:

A barrier layer is introduced as an intermediary between the copper film and the SOG material. This barrier layer prevents direct interaction between copper and SOG during high-temperature baking, thereby preventing copper oxidation and diffusion while still allowing the SOG to form a planarizing film on top.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier layer is formed in advance before applying the SOG material. This preliminary protective action ensures that when the SOG is subsequently baked at high temperature, the copper film is already protected and cannot undergo oxidation or diffusion reactions.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If copper film is used for low resistance, then electrical conductivity is improved, but copper diffusion into SOG material increases during baking

Engineering Contradiction:
Improveelectrical conductivityVSAvoidcopper diffusion
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

The barrier layer serves as a mediator that allows the copper film to maintain its low-resistance property while preventing copper atoms from diffusing into the SOG material during the baking process. The barrier layer is impermeable to copper diffusion but permits the copper film to function electrically.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Shape

If SOG material is baked at high temperature for planarization, then surface flatness is improved, but dielectric constant increases reducing insulation performance

Engineering Contradiction:
Improvesurface flatnessVSAvoidinsulation performance
Core Design Contradiction:
ShapeVSReliability

Solution Approach 1:

The barrier layer acts as a protective intermediary that prevents direct chemical reactions between the SOG material and the copper film during high-temperature baking. This isolation allows the SOG to achieve surface planarity without the harmful side effect of increased dielectric constant caused by copper diffusion.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces the increase in resistance of the gate electrode and dielectric constant of the SOG material, maintaining insulation performance and allowing for effective etching of the non-diffusive materials.

Implementation Method 1

the SOG material undergoes a dehydration polymerization reaction to produce moisture

Methodology Applied
Scientific EffectDehydration polymerization:

Implementation Method 2

copper can be prevented from diffusing from the second conductive film into the SOG material due to the baking

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS9087749B2Active matrix substrate, and display panel
Publication Date: 2015.07.21 SHARP KK
  • US9087749B2 patent drawing
  • US9087749B2 patent drawing
  • US9087749B2 patent drawing

AI summary

An active matrix substrate (20a) includes a gate electrode (25) formed on an insulating substrate (10a), and a planarizing film (26) formed on the gate electrode (25) and made of a baked SOG material. The gate electrode (25) is a multilayer film including a first conductive film (27) formed on the insulating substrate (10a) and made of a metal except copper, a second conductive film (28) formed on the first conductive film (27) and made of copper, and a third conductive film (29) formed on the second conductive film (28) and made of the metal except copper.