Gate Electrode Curving Prevention in Semiconductor Devices
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Solution Overview
Problem
As semiconductor devices are miniaturized, the gate electrode can curve toward the semiconductor substrate during oxide film formation, leading to short circuits between the gate electrode and source/drain regions due to the lack of a depressed portion in the insulating layer over the gate electrode.
Innovation Solution
A first insulating layer with a silicon nitride film having a depressed portion is formed over the gate electrode, which suppresses the curving of the gate electrode and prevents short circuits by maintaining the distance between the gate electrode and source/drain regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate electrode is miniaturized to increase integration density, then the device can achieve higher integration and miniaturization, but the gate electrode becomes prone to curving toward the source/drain regions during oxide film formation, causing short circuits
Solution Approach 1:
A depressed portion is formed in the insulating layer over the gate electrode before oxide film formation. This preliminary structural preparation prevents the gate electrode from curving toward the source/drain regions during subsequent oxide film formation, thereby avoiding short circuits while maintaining miniaturization benefits
Solution Approach 2:
The depressed portion in the insulating layer acts as an intermediary structural feature that modifies the stress distribution and physical constraints on the gate electrode. This intermediary structure prevents direct contact between the curving gate electrode and source/drain regions, resolving the short circuit issue without compromising device miniaturization
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a main surface, a gate electrode formed on the main surface of the semiconductor substrate, a side-wall oxide film formed on a side wall of the gate electrode, a first insulating layer formed on the gate electrode and containing silicon nitride, and a second insulating layer formed between the gate electrode and the first insulating layer and containing silicon oxide.