Gate Electrode Cut Width Reduction for Semiconductor Cell Density
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving a high density of cells due to limitations in the width of gate electrode cuts, which restricts the miniaturization and expansion of semiconductor functionality.
Innovation Solution
A method of manufacturing semiconductor devices involves forming gate electrode lines with cuts that have a width smaller than the minimum threshold by using a lithographic process, allowing for the deposition and subsequent removal of gate electrode material to create narrower cuts, thereby reducing cell height and increasing cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to form gate electrode cuts, then the minimum cut width is limited by process resolution, but this limits the ability to reduce cell height and increase cell density
Solution Approach 1:
The gate electrode material is segmented into multiple sections by forming cuts through the gate electrode line. Multiple mandrels are positioned at different locations to create multiple cuts, dividing the gate electrode into separate segments that can be independently controlled and optimized for density.
Solution Approach 2:
Mandrels are introduced as intermediary structures to define the cut regions. The mandrels serve as temporary placeholders that guide the deposition and etching processes to create precise cuts in the gate electrode material, enabling sub-lithographic cut widths.
2Length of moving object
If the gate electrode cut width is reduced below the minimum threshold, then cell height can be reduced and cell density increased, but conventional lithographic processes cannot achieve such narrow cuts
Solution Approach 1:
The solution moves from a planar lithographic approach to a three-dimensional self-aligned process. By depositing gate electrode material conformally over mandrels and then performing anisotropic etching, the cut width is determined by the mandrel dimensions and deposition thickness rather than lithographic resolution, achieving sub-lithographic precision.
Solution Approach 2:
The mechanical lithographic patterning process is replaced with a deposition-based self-aligned process. Instead of using lithography to directly pattern the cuts, the patent uses physical vapor deposition or chemical vapor deposition to form the gate electrode material around mandrels, followed by selective removal, achieving precision beyond mechanical lithographic limits.
Data Source
AI summary
A method of manufacturing a semiconductor device includes providing a material above a substrate and respectively forming separate gate electrode lines on opposite sidewalls of the material. As such, a width of cut between the gate electrode lines can be minimized. This shortens a height of cell of the semiconductor device, increasing a cell density of the semiconductor device.