Gate Electrode Encapsulation for Reduced Contact Resistance
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Solution Overview
Problem
As integrated circuits shrink, the reduced size of transistor elements leads to increased electrical resistance in conductive contact elements due to decreased cross-sectional area, making it challenging to maintain acceptable electrical resistance characteristics and sufficient spacing between gate electrodes, especially at advanced technology nodes like 20 nm design.
Innovation Solution
The implementation of self-aligning contact elements and a full dielectric encapsulation of gate electrode stacks using multiple dielectric material layers, such as silicon nitride, to reduce electrical resistance and maintain adequate spacing between gate electrodes, even at aggressively scaled pitches below 100 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If feature sizes are decreased to enhance performance, then drive current capabilities and switching speeds are improved, but electrical resistance of conductive contact elements increases due to decreased cross-sectional area
Solution Approach 1:
The patent transitions from two-dimensional planar contacts to three-dimensional vertically-aligned contacts through self-aligning contact elements. The contact elements extend vertically through multiple dielectric layers to directly connect source/drain regions, increasing the effective contact area and reducing resistance without increasing lateral footprint.
Solution Approach 2:
The contact elements are nested within encapsulating dielectric structures that contain multiple dielectric layers. The contact elements pass through horizontally-extending portions of these nested dielectric layers, allowing vertical connection while being protected and positioned by the surrounding nested structure.
2Productivity
If pitch between adjacent transistors is decreased to increase integration density, then device functionality is enhanced, but spacing between gate electrodes becomes insufficient
Solution Approach 1:
The encapsulating dielectric structures perform multiple functions simultaneously: they encapsulate the gate electrode stacks, provide spacing between adjacent gates, and serve as templates for self-aligning contact elements. This self-service approach eliminates the need for separate spacing structures.
Solution Approach 2:
The encapsulating dielectric structures serve multiple purposes: gate encapsulation, inter-gate spacing, and contact element alignment templates. The horizontally-extending portions provide both structural separation and positioning references for subsequent contact formation processes.
3Reliability
If self-aligning contact elements are implemented, then electrical resistance is reduced, but device complexity increases due to multiple dielectric material layers
Solution Approach 1:
The encapsulating dielectric structures are formed in advance with horizontally-extending portions that pre-establish the positions and dimensions of future contact elements. This preliminary action guides subsequent contact formation without requiring complex alignment processes.
Solution Approach 2:
The horizontally-extending portions of the encapsulating dielectric structures serve as intermediary templates between the gate electrode stacks and the contact elements. They mediate the transition from gate definition to contact formation, providing a straightforward geometric reference for self-aligning contacts.
Data Source
AI summary
A semiconductor device includes a plurality of NMOS transistor elements, each including a first gate electrode structure above a first active region, at least two of the plurality of first gate electrode structures including a first encapsulating stack having a first dielectric cap layer and a first sidewall spacer stack. The semiconductor device also includes a plurality of PMOS transistor elements, each including a second gate electrode structure above a second active region, wherein at least two of the plurality of second gate electrode structures include a second encapsulating stack having a second dielectric cap layer and a second sidewall spacer stack. Additionally, the first and second sidewall spacer stacks each include at least three dielectric material layers, wherein each of the three dielectric material layers of the first and second sidewall spacer stacks include the same dielectric material.