Gate Electrode Etching for Leakage Current Control
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Solution Overview
Problem
The existing process for forming gate electrodes in semiconductor devices faces challenges in achieving uniform impurity concentration and film thickness, leading to increased depletion layers, leakage currents, and difficulties in optimizing sidewall spacer width due to simultaneous impurity ion implantation processes for gate and source/drain regions.
Innovation Solution
A method involving multiple etching conditions to form silicon films with controlled impurity concentrations, where a high-concentration first silicon film is etched in conjunction with a low-concentration second silicon film, using specific gas mixtures and etching ratios to maintain uniform pattern widths and prevent side etching, allowing for precise control of gate electrode dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the polysilicon film thickness is increased to ensure sufficient impurity concentration in the gate electrode, then the impurity concentration in the lower layer portion becomes insufficient and a depletion layer is increased, but increasing acceleration energy to introduce impurity at enough depth increases the amount of impurity breaking through the gate insulating film causing leakage current
Solution Approach 1:
The patent divides the single impurity implantation process into multiple sequential implantation steps with different acceleration energies and dosages. The first implantation uses lower energy to concentrate impurity in the gate electrode region, while subsequent implantations use progressively higher energies to reach deeper layers without excessive breakthrough, thereby segmenting the impurity distribution control
Solution Approach 2:
The patent systematically changes the acceleration energy and impurity dosage parameters across multiple implantation steps. By adjusting these parameters in a controlled sequence, the patent achieves optimal impurity concentration distribution in the gate electrode while preventing excessive impurity penetration that would cause leakage current through the gate insulating film
2Manufacturing precision
If the polysilicon film thickness is reduced to decrease depletion layer, then the effective film thickness of the gate insulating film is increased, but it becomes difficult to widen the width of the sidewall spacer
Solution Approach 1:
The patent applies different impurity concentrations to different regions of the polysilicon film structure. The gate electrode region receives higher impurity concentration to maintain conductivity with thinner film, while the sidewall regions benefit from the thinner overall film thickness that allows for wider spacer formation, achieving local optimization of both parameters
3Manufacturing precision
If acceleration energy is enhanced to introduce impurity into the thick polysilicon film at enough depth, then impurity concentration in the lower layer portion is improved, but the amount of impurity breaking through the gate insulating film is increased causing leakage current
Solution Approach 1:
The patent performs preliminary impurity implantation at lower acceleration energies before attempting deeper implantation. This preliminary action establishes a foundation of impurity concentration in the upper regions, allowing subsequent higher-energy implantations to add depth without excessive total impurity content that would cause breakthrough and leakage current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform widths of conductive patterns, suppresses side etching, and achieves the target line width of gate electrodes, thereby enhancing transistor performance by reducing leakage currents and optimizing film thickness.
Implementation Method 1
first etching the second silicon film in a depth such that the first silicon film is not exposed, in a first condition, second etching a remaining portion of the second silicon film and the first silicon film in a depth such that the first insulating film is not exposed, in a second condition
Data Source
AI summary
A method of manufacturing a semiconductor device has forming a first silicon film over the first insulating film, forming a second silicon film over the first silicon film, a first etching the second silicon film in a depth, which the first silicon film is not exposed, in first condition, a second etching a remaining portion of the second silicon film and the first silicon film in a depth, which the first insulating film is not exposed, in second condition which gives a higher vertical etching component ratio than the first condition; and a third etching a remaining portion of the first silicon film in third condition which an etching rate for the first silicon film is larger than an etching rate for the first insulating film as compared to the second condition, wherein an impurity concentration of a first conductivity type of the first silicon film is higher than an impurity concentration of first conductivity type of the second silicon film.