Non-Closed Loop Gate Electrode Structure for Etching Accuracy
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Solution Overview
Problem
In high-definition OLED display products, the increased line density of transistors in the non-display region leads to challenges in etching accuracy and position errors during the formation of double-gate transistors, resulting in incomplete etching and performance deviations.
Innovation Solution
A circuitry structure is designed with a functional transistor and a signal transmission line on a base substrate, featuring a non-closed loop gate electrode pattern structure and a conductive connection member that prevents the formation of a closed-loop structure during etching, ensuring accurate etching and high-density wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the line density of transistors is increased in the non-display region, then the integration degree and high-definition requirements are met, but the etching accuracy deteriorates and position errors increase
Solution Approach 1:
The gate electrode pattern is segmented into multiple sections with spacing between them, forming a non-closed loop structure. This segmentation prevents the formation of closed-loop patterns that cause etching errors, while still providing the necessary electrical connectivity through conductive connection members at different layers.
Solution Approach 2:
The solution moves from a two-dimensional planar gate electrode pattern to a three-dimensional structure by introducing conductive connection members at different layers. The first conductive connection member connects the second ends of gate electrode patterns at a different layer, creating a vertical connectivity path that avoids the closed-loop problem in the planar layer.
2Productivity
If the line density of transistors is increased, then more transistors can be integrated, but incomplete etching occurs and transistor performance deviates
Solution Approach 1:
The gate electrode pattern is divided into multiple segments with gaps between them, preventing the formation of continuous closed-loop structures. This segmentation ensures complete etching by eliminating the closed-loop effect that causes etching inhibition, thereby ensuring consistent transistor performance across high-density integrations.
Solution Approach 2:
Conductive connection members serve as intermediaries to connect the segmented gate electrode patterns. These connection members are positioned at different layers and provide the necessary electrical connectivity without forming closed-loop structures in the etching layer, thus maintaining both high integration and performance reliability.
3Device complexity
If a closed-loop gate electrode pattern structure is used, then the transistor structure is compact, but etching errors occur due to the closed-loop formation
Solution Approach 1:
The closed-loop gate electrode pattern is segmented into multiple sections with intentional spacing between them. This segmentation breaks the closed-loop structure that causes etching errors, while the overall compactness is maintained through the use of conductive connection members that provide connectivity in a three-dimensional configuration.
Solution Approach 2:
The solution transitions from a two-dimensional closed-loop pattern to a three-dimensional non-closed loop structure. By introducing vertical connectivity through conductive connection members at different layers, the design maintains electrical connectivity while eliminating the planar closed-loop that causes etching failures.
Data Source
AI summary
The present disclosure provides a circuitry structure and a display substrate. The circuitry structure includes a base substrate, and a functional transistor and a signal transmission line arranged on the base substrate. The functional transistor includes a first conductive connection member, a first electrode, a second electrode, at least two gate electrode patterns and at least one active pattern. Orthogonal projections of the first electrode, the second electrode and the at least two gate electrode patterns onto the base substrate at least partially overlap with an orthogonal projection of the active pattern onto the base substrate, and first ends of the gate electrode patterns are coupled to each other. The first conductive connection member is arranged at a layer different from the gate electrode pattern, and coupled to second ends of the gate electrode patterns. The signal transmission line is coupled to the first conductive connection member.