Gate Electrode Isolation via Sidewall Spacer Cutting

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Solution Overview

Problem

The semiconductor manufacturing process faces challenges in forming gate electrodes with high precision, particularly at 45 nm or below, due to difficulties in etching small cuts between gate electrodes, which can lead to short circuits and require extremely high precision lithography, making it hard to satisfy the requirements of integration and isolation.

Innovation Solution

The method involves cutting off gate electrode lines after forming sidewall spacers and before the completion of the Front End of Line (FEOL) process, using techniques like Reactive Ion Etching or laser cut etching, to form electrically isolated gate electrodes, thereby simplifying the process and reducing the need for high precision Optical Proximity Correction (OPC).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If double-mask lithography is used to form gate electrodes, then gate electrode lines can be formed, but the cuts between gate electrodes become very small and difficult to fill with insulating material, causing short circuits

Engineering Contradiction:

Improvegate electrode line cut precisionVSAvoidelectrical isolation between gate electrodes

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent performs the gate electrode line cutting operation after forming sidewall spacers, which have already defined the precise locations where cuts are needed. The sidewall spacers serve as pre-formed masks that guide the cutting process, ensuring accurate and reliable isolation between gate electrodes without requiring extremely precise lithography.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If double-mask lithography with high precision is used, then gate electrode lines can be formed, but Optical Proximity Correction becomes extremely difficult and cannot satisfy the requirements of gate mask imaging and etching precision at 45 nm or below

Engineering Contradiction:

Improvegate mask imaging precisionVSAvoidlithography process complexity

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent divides the gate electrode formation process into separate stages: first forming continuous gate electrode lines, then later cutting them into individual electrodes. This segmentation of the process allows each step to be optimized independently, avoiding the need for extremely precise single-step lithography and reducing the complexity of Optical Proximity Correction requirements.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces sidewall spacers as an intermediary structure that facilitates the cutting process. These spacers act as self-aligned masks that simplify the lithography requirements by providing clear, well-defined boundaries for the cutting operation, eliminating the need for complex OPC at the cutting stage.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Manufacturing precision

If cuts between gate electrodes are made very small to achieve high precision, then gate electrode isolation can be improved, but the cuts become hard to fill with insulating material during sidewall spacer formation

Engineering Contradiction:

Improvegate electrode isolation precisionVSAvoidinsulating material filling ease

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

Instead of making small cuts first and then trying to fill them with insulating material, the patent inverts the sequence: it forms sidewall spacers first, which naturally create the necessary isolation, and then performs the cutting operation. This reversal of the conventional approach ensures that the insulating material filling step is not compromised by small cut dimensions.

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the precision of gate electrode line cuts, prevents short circuits, and simplifies the manufacturing process by allowing smaller cuts and improved sectional shapes of sidewall spacers, reducing the complexity of lithography and etching processes.

Implementation Method 1

cutting off the gate electrode lines by means of Reactive Ion Etching

Methodology Applied

Scientific EffectReactive Ion Etching: Plasma

Implementation Method 2

cutting off the gate electrode lines by means of ... laser cut etching

Methodology Applied

Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS8652884B2Semiconductor device structure and method for manufacturing the same

Publication Date: 2014.02.18 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD

AI summary

The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.