Gate Electrode Layer Design for Semiconductor Device Height Reduction
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Solution Overview
Problem
The increasing number of logic circuits in semiconductor devices necessitates a reduction in circuit cell height to achieve size reduction while maintaining efficient operation.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with a gate electrode layer that crosses over active regions, featuring a non-doped region between gate electrodes to reduce height and prevent leakage current, and utilizes thin film and bulk MISFETs with integral gate structures for power and reference potential distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of logic circuits is increased to achieve higher device function, then the device capability is improved, but the device size increases
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacked arrangement of circuit cells. Multiple circuit cells are vertically stacked above each other, utilizing the vertical dimension to increase device function without proportionally increasing the planar device area. This dimensional change allows higher integration density.
Solution Approach 2:
The patent implements nested structures where gate electrode layers are embedded within semiconductor regions, and multiple functional layers are stacked within a compact vertical space. The gate electrodes are positioned between source/drain regions in a nested configuration, maximizing space utilization.
2Area of stationary object
If the circuit cell height is reduced to achieve size reduction, then the device area is decreased, but the electrical insulation and leakage current control become more difficult
Solution Approach 1:
The patent introduces gate electrode layers as intermediary structures between adjacent source/drain regions in vertically stacked circuit cells. These gate electrodes serve as both functional switching elements and electrical insulation barriers, preventing leakage current between adjacent circuits while enabling compact vertical integration.
Solution Approach 2:
The patent employs composite material structures combining different semiconductor regions with varying conductivity types (n-type and p-type) arranged in alternating layers. This composite structure provides both the necessary electrical functionality and inherent insulation properties through the alternating conductivity type layers.
Data Source
AI summary
A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions . Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.