Gate Electrode Formation via Lift-Off and Electroless Plating
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Solution Overview
Problem
In high-frequency semiconductor devices, existing methods for forming gate electrodes on compound semiconductors like GaAs and GaN lead to substrate damage, footing issues, and inadequate gate height, resulting in degraded transistor characteristics and increased parasitic capacitance.
Innovation Solution
A method involving the formation of an insulation film with an opening, followed by a reverse-tapered first resist and metal deposition using vapor deposition or sputtering, subsequent lift-off, and electroless plating to grow a second metal, which eliminates the need for dry etching and lift-off, thereby reducing substrate damage and footing while ensuring gate electrode height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dry etching is used to remove the feeding layer film, then the gate electrode can be formed, but damage to the semiconductor substrate occurs leading to degradation in device characteristics
Solution Approach 1:
The patent extracts and removes the harmful dry etching step from the gate electrode formation process. Instead of using dry etching to remove the feeding layer film, the invention uses a lift-off method where a resist pattern is formed first, then the feeding layer is deposited and subsequently removed by lifting off the resist along with the deposited metal, eliminating substrate damage entirely
Solution Approach 2:
The patent introduces a resist pattern as an intermediary element that enables the formation and subsequent removal of the feeding layer without direct contact with the substrate. The resist serves as a temporary structure that facilitates metal deposition and then allows clean removal through lift-off, acting as a mediator between the metal deposition process and the final gate electrode formation
2Object-affected harmful factors
If an insulation film is sandwiched between the semiconductor substrate and gate electrode to avoid dry etching damage, then substrate damage is prevented, but parasitic capacitance increases causing degradation in transistor characteristics
Solution Approach 1:
The patent extracts and eliminates the insulation film from the gate electrode structure. By using the lift-off method, the invention achieves both substrate protection and parasitic capacitance reduction, removing the need for the insulating layer that previously caused harmful capacitive effects
Solution Approach 2:
The resist pattern serves as the intermediary that replaces the dual function previously performed by the insulation film. The resist protects the substrate during metal deposition and then enables clean removal, eliminating the need for a permanent insulating layer while maintaining substrate protection
3Object-affected harmful factors
If the lift-off method is used to form the gate electrode, then substrate damage is avoided, but footing occurs at the base of the gate electrode increasing parasitic capacitance
Solution Approach 1:
The patent applies local quality by creating a tapered resist pattern with different thicknesses at different locations. The resist is thicker at the base and tapers upward, providing enhanced protection and control at the critical base region where footing occurs, while allowing proper metal deposition and removal at the upper portions of the gate electrode
Solution Approach 2:
The patent changes the geometric parameters of the resist pattern, specifically creating a tapered profile with controlled thickness variation. This parameter change in the resist structure prevents the uniform thickness that causes footing, allowing the metal to be deposited and removed cleanly without forming unwanted lateral extensions
4Length of stationary object
If the thickness of the resist is increased to ensure gate electrode height during miniaturization, then gate height can be maintained, but the resist thickness cannot be increased due to miniaturization constraints
Solution Approach 1:
The patent applies local quality by creating a tapered resist pattern where the thickness varies locally - thicker at the base for structural integrity and metal removal control, and thinner at the top for proper gate electrode formation. This local variation in thickness allows the gate electrode to achieve sufficient height without requiring uniformly thick resist that would be incompatible with miniaturization
Solution Approach 2:
The patent transitions from considering only the vertical dimension of resist thickness to utilizing the lateral dimension as well, creating a tapered profile that varies thickness across the vertical axis. This dimensional approach allows the resist to provide adequate support for gate height while maintaining compatibility with miniaturized device dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses substrate damage, prevents footing, and ensures a sufficient gate electrode height, enhancing high-frequency device characteristics by reducing parasitic capacitance and improving gate resistance.
Implementation Method 1
forming a first metal on the opening section, the semiconductor substrate exposed via the opening section, and the first resist by a vapor deposition method or a sputtering method
Implementation Method 2
forming a first metal on the opening section, the semiconductor substrate exposed via the opening section, and the first resist by a vapor deposition method or a sputtering method
Implementation Method 3
causing the first metal to grow a second metal by an electroless plating method
Data Source
AI summary
Included are forming, on a semiconductor substrate, an insulation film having an opening section where an opening is formed, forming a first resist on the insulation film while avoiding the opening section and the semiconductor substrate exposed via the opening section, forming a first metal on the opening section, the semiconductor substrate exposed via the opening section, and the first resist by a vapor deposition method or a sputtering method, removing, by a lift-off method, the first resist and the first metal on the first resist, forming, on the insulation film, a second resist allowing the first metal to be exposed, causing the first metal to grow a second metal by an electroless plating method, and removing the second resist, where these processings are included in the listed order.