Semiconductor Gate Electrode Overlap Region Leakage Reduction

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Solution Overview

Problem

The miniaturization of semiconductor circuits leads to increased gate leakage current in anti-fuse elements, causing current dispersion and high resistance issues, which complicates circuit design and requires additional circuits or parallel arrangements to prevent inappropriate operation.

Innovation Solution

A semiconductor device design where the peripheral portions of the gate electrode and active region overlap, forming a smaller overlap region to reduce gate leakage current and prevent current dispersion, allowing for an ohmic connection without the need for additional circuits or process changes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the gate insulating film is thinned to miniaturize circuits, then circuit integration density is improved, but gate leakage current increases causing current dispersion and high resistance

Engineering Contradiction:
Improvecircuit integration densityVSAvoidgate leakage current
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The gate electrode is divided into a first gate electrode and a second gate electrode that are spatially separated by a first gap, with the active region divided into first and second active regions by a second gap. This segmentation reduces the overlap area between gate electrode and active region, thereby reducing gate leakage current while maintaining miniaturized circuit dimensions

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces specific gap regions (first gap between gate electrodes, second gap between active regions) that create localized non-overlapping zones. This local modification of the structure reduces gate leakage current in specific areas without affecting the overall miniaturization of the circuit

Inventive Principle:
Principle #3Local quality

2Reliability

If additional circuits or parallel arrangements are added to prevent high resistance, then reliability is improved, but device complexity and chip area increase

Engineering Contradiction:
Improveanti-fuse element reliabilityVSAvoidcircuit design complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The segmented gate electrode structure inherently prevents current dispersion through its geometric configuration. The non-overlapping gaps automatically concentrate current flow through the anti-fuse element without requiring additional protective circuits or parallel arrangements, making the structure self-regulating

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively reduces gate leakage current and improves the reliability of anti-fuse elements by concentrating the current flow, enabling reliable ohmic connections even with a thinned gate insulating film, without increasing processing complexity or chip size.

Implementation Method 1

a high electric field is applied between gate electrode 101 and diffusion layer 105 to destroy gate insulating film 104, causing short-circuiting

Methodology Applied
Scientific EffectElectrical breakdown: Avalanche Breakdown

Implementation Method 2

This connection operation allows a high current to flow through the destroyed part of gate insulating film 104 to provide energy, resulting in ohmic contact

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS8729642B2Semiconductor device comprising a gate electrode having an opening
Publication Date: 2014.05.20 LONGITUDE LICENSING LTD
  • US8729642B2 patent drawing
  • US8729642B2 patent drawing
  • US8729642B2 patent drawing

AI summary

A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.