Gate Electrode Planarization via CMP for Isolation Step Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device manufacturing, achieving uniformity in gate electrode heights is challenging due to step differences created by device isolation layers, leading to processing hardships and irregularities in subsequent steps.
Innovation Solution
A method involving sequential formation of insulation and conductive layers on a substrate with a device isolation layer, followed by planarization using chemical mechanical polishing to ensure all gate electrodes are at the same height, facilitating uniform processing and reducing the need for thick interlayer dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If device isolation layers are formed higher than the substrate surface to provide electrical isolation, then electrical isolation effectiveness is improved, but step differences are created causing non-uniform gate electrode heights and processing difficulties
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer over the device isolation layer before forming the gate electrode. This planarization layer pre-compensates for the height difference created by the elevated device isolation layer, ensuring that the gate electrode can be formed at a uniform height across the entire substrate surface, thereby resolving the contradiction between electrical isolation effectiveness and gate electrode height uniformity
2Manufacturing precision
If thicker interlayer dielectric layers are used to cover step differences, then surface planarity is improved, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent forms a planarization layer in advance to create a flat surface before subsequent processing steps. This preliminary planarization eliminates the need for thick interlayer dielectric layers to compensate for step differences, thereby reducing device complexity and the number of manufacturing steps while maintaining surface planarity
Solution Approach 2:
The patent extracts the planarization function into a separate, dedicated layer formed early in the process. By taking out the planarization requirement from the interlayer dielectric structure, the patent avoids the need for excessive dielectric thickness and reduces overall device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures processing uniformity and simplifies subsequent manufacturing steps by eliminating step differences, enhancing the reliability and consistency of semiconductor device characteristics.
Implementation Method 1
The planarizing may be performed prior to forming the gate electrode by a chemical mechanical polishing process
Data Source
AI summary
A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.