Gate Electrode Vertical Protrusion for Semiconductor Parasitic Capacitance
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Solution Overview
Problem
Semiconductor devices face challenges in achieving low parasitic capacitance and high electrical stability with increasing demands for smaller pitch sizes and denser integration, while maintaining reliability and cost-effectiveness.
Innovation Solution
The semiconductor device design includes a gate electrode with a vertical protrusion directly connected to a gate contact on an active region, allowing for improved spacing between the gate and source/drain contacts, which is achieved through a specific fabrication method involving multiple mask patterns and etching processes to form recesses and capping patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch size is reduced to achieve denser integration, then the device integration density is improved, but the parasitic capacitance increases and electrical stability deteriorates
Solution Approach 1:
The gate electrode is designed with a vertical protrusion extending downward into the active region, transitioning from a purely lateral layout to a three-dimensional structure. This vertical dimension allows the gate contact to be positioned closer to the source/drain contacts in the lateral plane while maintaining adequate spacing through the vertical offset, thereby reducing parasitic capacitance even at smaller pitch sizes
Solution Approach 2:
The gate electrode is segmented into two distinct portions: a first portion at a higher level and a second portion (vertical protrusion) extending downward at a lower level. This segmentation allows the gate contact to connect at the lower level while source/drain contacts remain at the higher level, creating natural electrical isolation that reduces parasitic capacitance between gates and sources/drains
2Reliability
If the margin between gate contact and source/drain contact is increased to improve electrical stability, then the parasitic capacitance is reduced, but the device integration density decreases
Solution Approach 1:
By utilizing the vertical dimension with the gate electrode protrusion, the design achieves adequate electrical spacing without requiring increased lateral margin. The gate contact connects to the lower-level protrusion while source/drain contacts remain at the higher level, enabling dense lateral packing while maintaining electrical stability through vertical separation
3Ease of manufacture
If a conventional gate electrode structure is used, then the manufacturing process is simpler, but the margin between gate and source/drain contacts is insufficient
Solution Approach 1:
The vertical protrusion of the gate electrode is formed during the gate electrode fabrication process itself, before subsequent contact formation steps. This preliminary creation of the protruding structure ensures that the gate contact will naturally have adequate spacing from source/drain contacts, with the spacing already built into the gate electrode geometry rather than requiring precise control in later alignment steps
Data Source
AI summary
A semiconductor device includes an active pattern extending in a first horizontal direction on a substrate, a gate electrode extending in a second horizontal direction across the active pattern, and including a first portion, and a second portion protruding upward from the first portion in a vertical direction, a capping pattern extending in the second horizontal direction on the gate electrode, and a gate contact disposed on the second portion of the gate electrode, overlapping the active pattern, and penetrating the capping pattern to connect the gate electrode.