Semiconductor Gate Electrode Recessed Top Surface Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high reliability and high-speed performance due to increased complexity and integration density, particularly in reducing parasitic capacitance between the gate electrode and dielectric structures, which affects operating speed and electrical characteristics.
Innovation Solution
The semiconductor device design includes a gate electrode with a recessed top surface between adjacent channel patterns, positioned lower than the contact, and a gate capping pattern covering the gate electrode and mask pattern, which reduces parasitic capacitance by ensuring the gate electrode is lower than the contact, thereby enhancing operating speed and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate electrode is positioned at the same level as or higher than the contact, then the manufacturing process is simpler, but parasitic capacitance increases reducing operating speed
Solution Approach 1:
The gate electrode structure is segmented into multiple portions with different heights. The first gate electrode portion is positioned at a first height from the substrate, while the second gate electrode portion is positioned at a second height that is lower than the first height. This segmentation allows the gate electrode to be positioned lower than the contact, reducing parasitic capacitance and improving operating speed, while maintaining manufacturability through controlled segment formation.
Solution Approach 2:
Different portions of the gate electrode are given different local properties in terms of height and position. The first gate electrode portion maintains a standard height for normal operation, while the second gate electrode portion is locally reduced in height to position it below the contact level, specifically targeting the reduction of parasitic capacitance in critical areas without affecting overall device functionality.
2Productivity
If integration density is increased to meet demand, then more functionality is achieved, but parasitic capacitance between gate electrode and dielectric structures increases
Solution Approach 1:
The solution moves from a two-dimensional planar gate electrode configuration to a three-dimensional stepped configuration. By utilizing the vertical dimension to create multiple height levels, the gate electrode can maintain high integration density in the horizontal plane while reducing parasitic capacitance through vertical positioning of the second gate electrode portion below the contact level.
Data Source
AI summary
A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.