Gate Electrode Recessing via Selective Wet Etching
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Solution Overview
Problem
During the fabrication of semiconductor devices, materials forming gate barrier layers often remain on side surfaces not in contact with the gate barrier layer, leading to defects and loss of the gate insulating layer, especially when recessing the gate barrier and electrode layers, which can result in surface dispersion and increased leakage current.
Innovation Solution
A method involving a dry etching process followed by two wet etching processes using specific etchant compositions to recess the gate barrier and electrode layers, ensuring minimal surface dispersion and preventing material accumulation on non-contact surfaces, while increasing the distance between the gate barrier layer and impurity layers to reduce channel length and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single etching process is used to recess the gate barrier layer and gate electrode, then the process is simple and fast, but material remains on side surfaces not in contact with the gate barrier layer causing defects
Solution Approach 1:
The etching process is divided into three distinct stages: dry etching for initial recess, first wet etching for selective gate electrode removal, and second wet etching for selective gate barrier layer removal. Each stage targets specific materials with different etchants, preventing material accumulation on non-contact side surfaces while maintaining efficient overall processing.
Solution Approach 2:
Different etchants are applied at different stages to achieve selective removal: the first wet etchant specifically targets the gate electrode material, while the second wet etchant specifically targets the gate barrier layer material. This localized chemical action ensures precise material removal without affecting adjacent structures.
2Manufacturing precision
If aggressive etching is used to completely remove material, then side surface defects are prevented, but gate insulating layer is lost
Solution Approach 1:
The etching process parameters are carefully controlled at each stage: dry etching uses plasma parameters for anisotropic etching, first wet etching uses specific chemical composition and temperature for selective gate electrode removal, and second wet etching uses different chemical parameters for gate barrier layer removal. These parameter changes enable precise material removal without damaging the gate insulating layer.
Solution Approach 2:
The gate insulating layer serves as an intermediary protective layer throughout the etching process. The conformal coverage ensures that etchants are selectively removed from side surfaces without penetrating through the insulating layer, thus preventing insulating layer loss while still achieving side surface cleanliness.
3Reliability
If gate barrier layer and gate electrode are recessed deeply, then channel length is reduced and leakage current decreases, but surface dispersion increases
Solution Approach 1:
The recessing process is performed in periodic stages rather than continuously: dry etching creates initial recess, followed by first wet etching for gate electrode removal, then second wet etching for gate barrier layer removal. This periodic action allows controlled material removal at each stage, maintaining surface uniformity while achieving the desired recess depth for reduced leakage current.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively minimizes surface dispersion, prevents defects, and reduces leakage current by ensuring precise control over the recessing of gate barrier and electrode layers, thereby enhancing the reliability and yield of semiconductor devices.
Implementation Method 1
performing a dry etching process, a first wet etching process, and a second wet etching process to recess a gate barrier layer and a gate electrode
Implementation Method 2
removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant
Implementation Method 3
removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth.