Gate Electrode Riding Source/Drain Layer for Parasitic Resistance Reduction
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Solution Overview
Problem
Current semiconductor devices with MISFETs face challenges in improving performance and reliability, particularly in achieving effective source/drain semiconductor layer formation using epitaxial growth methods, which often result in parasitic resistance and electrical characteristic degradation.
Innovation Solution
The solution involves forming a source/drain semiconductor layer on a substrate with the end parts of the gate electrode riding onto the semiconductor layer, using a dummy gate structure and epitaxial growth, followed by the removal of the dummy gate and sidewall films to create a trench for the gate electrode, allowing for improved overlap with the source/drain region and reduced parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source/drain semiconductor layer is formed using an epitaxial growth method, then the performance and reliability of the semiconductor device are improved, but parasitic resistance increases and electrical characteristics degrade
Solution Approach 1:
The gate electrode end parts are extended onto the source/drain semiconductor layer in advance during the formation process. This preliminary action of creating overlap structure before final device assembly reduces parasitic resistance in the source/drain regions while maintaining the benefits of epitaxial growth for device reliability.
Solution Approach 2:
The gate electrode is designed to extend in the vertical dimension onto the source/drain layer, creating a three-dimensional overlap structure. This dimensional extension allows the gate electrode to make contact with the source/drain region in addition to the horizontal plane, reducing parasitic resistance through increased contact area while preserving the epitaxial growth advantages.
2Object-generated harmful factors
If the gate electrode end parts ride onto the source/drain semiconductor layer, then parasitic resistance is reduced and on-current increases, but the device structure becomes more complex
Solution Approach 1:
The overlap structure is created during the preliminary stages of device formation, integrating the gate electrode extension into the source/drain layer formation process. This preliminary action incorporates the complexity reduction by combining multiple functions into a single integrated structure rather than adding separate components later.
Solution Approach 2:
The gate electrode structure is merged with the source/drain semiconductor layer by extending the gate electrode onto the source/drain region. This merging combines the gate function with direct electrical contact to the source/drain, reducing parasitic resistance while consolidating structural elements to minimize overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of semiconductor devices by reducing parasitic resistance, increasing on-current, and improving electrical characteristics while maintaining a thinner gate insulating film thickness.
Implementation Method 1
a source/drain formation semiconductor layer is formed on the substrate by, for example, an epitaxial technique
Data Source
AI summary
The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.