Gate Electrode Segmentation for Parasitic Transistor Control
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Solution Overview
Problem
Semiconductor devices experience undesired humps in drain current due to parasitic transistors formed on the edge portions of active regions near the interface with isolation regions, affecting gate voltage control.
Innovation Solution
A semiconductor device design with a gate electrode extending across both the active and isolation regions, featuring a center gate portion doped with impurities and undoped or differently doped edge gate portions, along with a gate insulating layer, to prevent parasitic transistor activation and reduce threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate electrode structure is used, then the device structure is simple, but parasitic transistors are formed on edge portions causing hump in drain current
Solution Approach 1:
The gate electrode is divided into three distinct segments: a first gate electrode portion extending over the active region, a second gate electrode portion extending over the isolation region, and a third gate electrode portion connecting them. This segmentation allows independent optimization of each portion to prevent parasitic transistor formation while maintaining overall gate functionality.
Solution Approach 2:
Different regions of the gate electrode are given different properties: the first portion has dimensions optimized for active region control, the second portion has reduced dimensions or different material composition to minimize parasitic effects at the isolation region interface, and the third portion provides electrical connection. This local differentiation eliminates the hump phenomenon while preserving necessary gate control.
2Reliability
If the gate electrode extends into the isolation region, then parasitic transistor formation is prevented, but the manufacturing process becomes more complex
Solution Approach 1:
The gate electrode structure is designed with predetermined dimensions and configurations for each portion before fabrication. The first, second, and third portions are planned with specific width, length, and material properties in advance, allowing standard semiconductor manufacturing processes to be used without requiring complex post-fabrication adjustments or additional processing steps.
3Ease of manufacture
If the gate electrode has uniform dimensions, then manufacturing is easier, but threshold voltage control is reduced
Solution Approach 1:
The gate electrode employs local quality variations where the first portion has dimensions optimized for strong gate control over the active region, the second portion has reduced dimensions to minimize parasitic capacitance and threshold voltage shifts at the isolation interface, and the third portion provides electrical connection. This localized differentiation enables precise threshold voltage control while using standard manufacturing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively prevents the hump phenomenon in drain current, ensuring stable gate voltage control and improved junction breakdown voltage, as evidenced by comparable electrical characteristics to comparative devices without the hump issue.
Implementation Method 1
a gate insulating layer disposed between the active region and the gate electrode
Implementation Method 2
a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion
Data Source
AI summary
One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.