Gate Electrode Structure for Semiconductor Devices
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Solution Overview
Problem
The corner rounding phenomenon in gate electrodes of MIS transistors leads to increased contact resistance and reduced driving power due to misalignment and interference of diffracted light during photolithography, complicating mask pattern correction and increasing chip area.
Innovation Solution
A semiconductor device structure where the gate electrodes have regions with varying film thickness and pattern widths on the isolation and active regions, allowing for suppression of corner rounding without using Optical Proximity Effect Correction (OPC), and a manufacturing method involving specific mask patterns and etching processes to form these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the line width of gate electrodes is increased in gate contact regions to reduce contact resistance, then contact resistance decreases, but corner rounding phenomenon occurs due to optical interference during photolithography
Solution Approach 1:
The gate electrode is divided into multiple regions with different line widths: a first region over the active region with a smaller line width, and a second region over the insulating film with a larger line width. This segmentation allows optimization of contact resistance in the second region while maintaining manufacturing precision in the first region, resolving the contradiction between reducing contact resistance and preventing corner rounding.
2Manufacturing precision
If OPC (Optical Proximity Effect Correction) is applied to correct mask pattern deformation, then line width precision improves, but device complexity and calculation time increase
Solution Approach 1:
Instead of applying complex OPC to correct the mask pattern after design, the invention inverts the approach by directly designing the mask pattern with the desired final dimensions. The mask pattern is created to form gate electrodes with different line widths in different regions, eliminating the need for post-design correction and reducing overall device complexity.
3Area of stationary object
If gate contact regions are arranged closer to active regions to reduce chip area, then chip area decreases, but corner rounding phenomenon worsens due to increased optical interference
Solution Approach 1:
The gate electrode is designed with different line width characteristics in different regions: the first region over the active region has a smaller line width with precise rectangular contours, while the second region over the insulating film has a larger line width. This local quality differentiation allows gate contact regions to be arranged closer to active regions, reducing chip area, while maintaining manufacturing precision where it is most critical.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents corner rounding, reduces contact and wiring resistance, and enables closer arrangement of gate contact and wiring regions to active areas, enhancing transistor integration and performance without the complexity of OPC.
Implementation Method 1
coherent light is irradiated to a photosensitive material called a resist above a semiconductor substrate through a photomask made of a mask-patterned shielding material on a glass substrate so that diffracted light passing through the photomask is one-to-one projected or reduction-projected through a projection lens
Implementation Method 2
diffracted light passing through the photomask is one-to-one projected or reduction-projected through a projection lens
Implementation Method 3
forming a gate electrode by etching the gate electrode formation film with the use of the resist pattern and the mask pattern as masks
Data Source
AI summary
A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.