Polysilicon Gate Electrode Silicide Resistance
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Solution Overview
Problem
In semiconductor devices with polymetal gate structures, the formation of metal silicide layers increases resistance, and the thinning of silicon layers complicates impurity diffusion, leading to degraded operation characteristics.
Innovation Solution
A semiconductor device structure with a dual gate structure, where the gate electrodes consist of a silicon layer doped with impurities and a metal-containing layer, with a second silicon layer that is either undoped or doped with a conductive type opposite to the first silicon layer, to prevent impurity diffusion into the silicide layer while maintaining low resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is formed directly on the polysilicon layer to reduce gate resistance, then the gate resistance is reduced, but a metal silicide layer forms during thermal treatment which increases resistance and degrades device operation speed
Solution Approach 1:
A silicon nitride barrier layer is introduced between the polysilicon layer and the metal layer to prevent direct reaction. This intermediary layer blocks the formation of high-resistance metal silicide while allowing the metal layer to maintain low resistance, thus resolving the contradiction between reducing gate resistance and preventing harmful silicide formation
Solution Approach 2:
The formation conditions of the silicon nitride layer are optimized (thickness control, deposition parameters) to achieve the right balance: thin enough to allow electrical function but sufficient to prevent complete reaction between metal and polysilicon during thermal treatment, thereby controlling the resistance characteristics
2Length of moving object
If a silicon layer is thinned to reduce device size, then the device size is reduced, but impurity implantation becomes difficult and impurity diffusion control becomes complex, degrading operation characteristics
Solution Approach 1:
The gate electrode is segmented into multiple functional layers: polysilicon layer, silicon nitride barrier layer, and metal layer. This segmentation allows each layer to perform its specific function - the polysilicon provides the base structure, the silicon nitride controls impurity diffusion, and the metal reduces resistance - thereby maintaining operation characteristics despite thinning the overall structure
Solution Approach 2:
A composite gate electrode structure is created combining polysilicon and metal layers separated by a silicon nitride barrier. This composite structure enables simultaneous achievement of low resistance (from metal), controlled impurity diffusion (from silicon nitride barrier), and sufficient impurity supply to the polysilicon, maintaining operation characteristics in thinned devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures sufficient impurity supply to the silicon layer without increasing gate electrode resistance, effectively suppressing impurity diffusion and maintaining high-speed device operation.
Implementation Method 1
a silicon layer formed in contact with the gate insulating film and doped with an impurity
Implementation Method 2
the metal layer reacts with the polysilicon layer in a high temperature thermal treatment to form a metal silicide layer
Implementation Method 3
a silicon nitride layer which prevents an impurity from diffusing
Implementation Method 4
it is hard to implant impurity (e.g., boron) into the silicon layer
Data Source
AI summary
A semiconductor device includes an N-channel transistor having an N-type gate electrode and a P-channel transistor having a P-type gate electrode which are formed on a semiconductor substrate. The P-type gate electrode includes a first silicon layer formed as the lowest layer, and doped with a P-type impurity; a second silicon layer formed on the first silicon layer; and a metal containing layer formed on the second silicon layer. The N-type gate electrode includes a third silicon layer formed as the lowest layer and doped with an N-type impurity; a fourth silicon layer formed on the third silicon layer; and a metal containing layer formed on the fourth silicon layer. At least one of the second silicon layer and the fourth silicon layer is doped with no impurity or an impurity of a conductive type opposite to that of the impurity in a corresponding one of the first silicon layer and third silicon layer.