Gate Electrode Formation via Double Exposure and Spacer Shrink
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Solution Overview
Problem
The existing two-step patterning process for forming gate electrode structures in semiconductor devices faces challenges with reduced scalability and controllability, particularly in defining the gate width, as device dimensions continue to shrink, leading to significant device variations and complexity in lithography and etch processes.
Innovation Solution
A double exposure double etching sequence is employed, where a mask opening is formed with reduced lateral dimensions by using spacer elements on inner sidewalls to define circuit features, allowing for superior controllability and scalability in defining both gate length and width, using deposition and anisotropic etch techniques to achieve uniformity and reduce process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-step patterning process is used to form gate electrode structures, then gate length can be defined, but gate width control and scalability deteriorate as device dimensions shrink
Solution Approach 1:
The patent segments the patterning process into distinct steps: first forming mask features defining gate length, then forming a mandrel layer and openings to define gate width. This segmentation allows independent optimization of length and width definition, resolving the contradiction between maintaining precision in one dimension while adapting to scaling in another.
Solution Approach 2:
The patent introduces a vertical dimension by forming a mandrel layer (e.g., silicon nitride) beneath the mask layer and using openings through this layer to define gate width. This dimensional approach enables precise width control independent of the lateral lithography process used for length definition, improving scalability.
2Productivity
If device dimensions are reduced to achieve higher integration density, then productivity improves, but manufacturing precision deteriorates due to process variations
Solution Approach 1:
The patent employs self-aligned processes where the mandrel layer and openings automatically define the gate width position relative to the mask features. This self-alignment eliminates the need for additional lithography alignment steps, maintaining precision while enabling scaling for higher productivity.
Solution Approach 2:
The patent changes the physical state and properties of materials through the process sequence: forming a mandrel layer with specific etch selectivity, creating openings with controlled dimensions, and using these as templates for gate electrode formation. These parameter changes enable precise dimension control at scaled sizes.
3Manufacturing precision
If complex lithography techniques are used to print features below wavelength, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent divides the patterning function into separate layers: the mask layer handles length definition through conventional lithography, while the mandrel layer with openings handles width definition through simpler deposition and etch processes. This segmentation reduces overall process complexity while maintaining precision.
Solution Approach 2:
The mandrel layer acts as an intermediary structure that translates the mask feature pattern into precisely defined gate width openings. This intermediate layer simplifies the overall process by decoupling the complex lithography step from the width definition step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of gate electrode structures with precise gate length and reduced lateral distance in the width direction, enhancing device uniformity and reducing overall process complexity compared to conventional methods.
Implementation Method 1
forming a spacer element on inner sidewalls of the mask opening so as to reduce the first width
Implementation Method 2
forming a mask feature in the mask layer by using the resist mask feature and the mask opening
Data Source
AI summary
When forming complex gate electrode structures, a double exposure double etch strategy may be applied, in which the lateral distance in the width direction of the gate electrode structures may be defined prior to forming mask features for defining the gate length. In this case, the width dimension of the mask opening may be adjusted on the basis of a spacer element, which may thus allow providing a reduced dimension on the basis of well-established process techniques.