Gate Electrode Strip Segmentation for Threshold Voltage Control

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Solution Overview

Problem

Conventional pre-doping processes in metal-oxide-semiconductor (MOS) devices result in lateral diffusion of dopants, leading to fluctuation in threshold voltages and limitations in device performance, especially in small-scale integrated circuits.

Innovation Solution

A semiconductor structure and method involving a gate electrode strip with a recessed portion over the insulating region between well regions, where the thickness of this portion is less than the other portions, reducing inter-diffusion of pre-doped impurities and improving threshold voltage control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If pre-gate doping process is used to increase dopant concentration at the interface, then depletion layer is eliminated and saturation current is improved, but lateral diffusion of dopants occurs causing threshold voltage fluctuation

Engineering Contradiction:
Improvesaturation currentVSAvoidthreshold voltage
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate electrode strip is divided into three portions: a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. The third portion has a reduced thickness compared to the first and second portions. This segmentation allows dopants to be concentrated at the interfaces between the gate electrode and gate dielectric over the well regions while preventing lateral diffusion into adjacent regions by the thinner third portion acting as a barrier.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different portions of the gate electrode strip are given different thicknesses to serve different functions. The first and second portions have sufficient thickness to provide adequate dopant concentration for eliminating depletion layers and ensuring proper device operation. The third portion has reduced thickness specifically to prevent lateral inter-diffusion of dopants between adjacent NMOS and PMOS devices, thereby maintaining local dopant purity and threshold voltage stability.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If polysilicon layer thickness is reduced to prevent lateral diffusion, then threshold voltage stability is improved, but dopant concentration at the interface may be insufficient

Engineering Contradiction:
Improvethreshold voltageVSAvoiddopant concentration
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The gate electrode strip is segmented into regions with different thicknesses. The first and second portions have greater thickness to ensure sufficient dopant concentration at the interfaces for eliminating depletion layers, while the third portion has reduced thickness to prevent lateral diffusion. This segmentation allows both requirements to be satisfied simultaneously in different locations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The gate electrode structure is prepared with varying thicknesses before the doping process. This preliminary structural preparation ensures that when dopants are introduced, they will be properly concentrated at the interfaces in the first and second portions while the thinner third portion already in place will prevent lateral diffusion during subsequent thermal processing.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If conventional pre-doping process is used, then dopant concentration is increased, but inter-diffusion between adjacent devices occurs causing device performance degradation

Engineering Contradiction:
Improvedopant concentrationVSAvoiddevice performance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The gate electrode strip is segmented with a thinner third portion over the insulating region that acts as a physical barrier to prevent inter-diffusion of dopants between adjacent NMOS and PMOS devices. This allows high dopant concentrations to be achieved in the first and second portions without the harmful inter-diffusion that occurs in conventional uniform thickness structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The third portion of the gate electrode strip with reduced thickness acts as an intermediary barrier between the first and second portions over adjacent well regions. This intermediate structure prevents direct lateral diffusion pathways between dopants in adjacent devices while still allowing the dopants to be present at high concentrations in their respective regions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces inter-diffusion of dopants, enhances threshold voltage stability, and allows for further down-scaling of integrated circuits while maintaining improved device matching and performance.

Implementation Method 1

a gate electrode strip on the gate dielectric and extending from over the first well region to over the second well region. The gate electrode strip includes a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. A thickness of the third portion is substantially less than the thicknesses of the first and the second portions.

Methodology Applied
Scientific EffectPhysical barrier effect:

Data Source

PatentUS7812400B2Gate strip with reduced thickness
Publication Date: 2010.10.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US7812400B2 patent drawing
  • US7812400B2 patent drawing
  • US7812400B2 patent drawing

AI summary

A semiconductor structure with reduced inter-diffusion is provided. The semiconductor structure includes a semiconductor substrate; a first well region in the semiconductor substrate; a second well region in the semiconductor substrate; an insulating region between and adjoining the first and the second well regions; a gate dielectric layer on the first and the second well regions; and a gate electrode strip on the gate dielectric and extending from over the first well region to over the second well region. The gate electrode strip includes a first portion over the first well region, a second portion over the second well region, and a third portion over the insulating region. A thickness of the third portion is substantially less than the thicknesses of the first and the second portions.