Gate Electrode Undercut Structure for Poly-Si/WN Interface Protection
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Solution Overview
Problem
The exposure of the sidewall interface between the poly-Si and WN layers during the etching process in semiconductor devices with a poly-metal structure leads to the formation of an insulation layer during re-oxidation, increasing gate resistance and causing signal delays in high-frequency operations.
Innovation Solution
A method involving sequential etching processes with specific conditions, including forming a gate insulation layer, etching the metal and silicon layers, creating an undercut beneath the metal layer, and performing a gate re-oxidation process to prevent the capping layer from having a small thickness on the interface, thereby preventing the formation of an insulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etching process is used to form gate patterns, then the gate electrode structure can be formed, but the sidewall of the poly-Si/WN interface becomes exposed due to negative slope, causing insulation layer formation and increased gate resistance
Solution Approach 1:
The patent performs a preliminary etching process to form an undercut structure beneath the metal layer before depositing the capping layer. This preliminary action creates a geometric configuration where the capping layer can overlap the poly-Si/WN interface, ensuring complete coverage and preventing oxidation at the critical interface region, thereby maintaining low gate resistance.
Solution Approach 2:
The patent introduces a horizontal dimension solution by creating an undercut structure that extends laterally beneath the metal layer. This dimensional change allows the capping layer to wrap around and cover the sidewall interface from a different spatial perspective, effectively protecting the interface without requiring vertical thickness increase.
2Reliability
If the capping layer thickness is increased to protect the interface, then oxidation prevention improves, but the etching selectivity requirements become more stringent and process complexity increases
Solution Approach 1:
The undercut structure is formed as a preliminary step that simplifies subsequent capping layer deposition. By pre-configuring the geometric relationship between layers, the process reduces the need for complex multi-step etching sequences and allows the capping layer to be deposited in a single step with standard thickness, reducing overall process complexity.
Solution Approach 2:
The patent modifies the etching parameters to achieve selective removal of the poly-Si layer while preserving the metal layer. By adjusting etching conditions such as plasma chemistry, power, and gas flow rates, the process achieves the required selectivity without increasing overall process complexity, allowing the undercut formation to proceed efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents the increase in gate resistance by ensuring the sidewall interface remains protected from oxidation, maintaining low resistance and preventing signal delays.
Implementation Method 1
performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer
Implementation Method 2
performing a gate re-oxidation process to cure plasma damage and micro-trench generated in the gate insulation layer that is exposed when forming the second pattern
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a gate insulation layer over a substrate, sequentially forming a silicon layer and a metal layer over the gate insulation layer, performing a first gate etching process to etch the metal layer using a gate hard mask layer, formed on the metal layer, as an etch barrier, and then partially etch the silicon layer, thereby forming a first pattern, performing a second gate etching process to partially etch the silicon layer, thereby forming an undercut beneath the metal layer, forming a capping layer on both sidewalls of the first pattern including the undercut, performing a third gate etching process to etch the silicon layer to expose the gate insulation layer using the gate hard mask layer and the capping layer as an etch barrier, thereby forming a second pattern, and performing a gate re-oxidation process.