Composite Gate Electrode Work Function Tuning
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Solution Overview
Problem
The degradation of polysilicon gate electrodes in advanced transistors leads to limitations in improving or optimizing threshold voltages for NMOS and PMOS transistors, hindering the achievement of lower power consumption and higher operating speeds in semiconductor devices.
Innovation Solution
A method involving the formation of multiple metal-containing layers on a semiconductor substrate, followed by annealing processes with reducing or oxidizing gases to adjust the effective work function of these layers, allowing for the precise adjustment of threshold voltages in transistors by controlling the concentration of nitrogen or oxygen, thereby enhancing the reliability and performance of CMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If polysilicon gate electrodes are used in advanced transistors, then the transistor structure is simple and manufacturing is easier, but the drive current degrades due to polysilicon depletion
Solution Approach 1:
The patent uses composite gate electrode structures combining metal layers (such as tungsten, titanium nitride, or tantalum nitride) with dielectric layers to replace traditional polysilicon gate electrodes. This composite approach maintains manufacturing feasibility while eliminating polysilicon depletion effects and enabling precise threshold voltage control through metal layer composition and thickness adjustment.
Solution Approach 2:
The patent changes the material parameters of the gate electrode from polysilicon to various metals and metal nitrides, each with different work functions. By selecting specific metal materials and controlling their thickness, the threshold voltage can be precisely adjusted to optimize both drive current and power consumption characteristics.
2Ease of manufacture
If polysilicon gate electrodes are used, then the manufacturing process is simpler, but the threshold voltage optimization is limited
Solution Approach 1:
The patent employs composite gate structures with multiple metal layers and dielectric layers that can be independently tuned. This allows precise control of threshold voltage through material selection and layer thickness adjustment while maintaining a manufacturing process compatible with existing CMOS technology.
Solution Approach 2:
The patent enables different threshold voltages to be achieved in different regions of the semiconductor device by locally adjusting the metal layer composition, thickness, or stacking sequence. This allows simultaneous optimization of NMOS and PMOS transistors with different voltage requirements within the same integrated circuit.
3Manufacturing precision
If multiple metal-containing layers with annealing processes are used, then threshold voltage precision is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent achieves precise threshold voltage control by adjusting parameters such as metal layer thickness, material composition, and annealing temperature. These parameter optimizations allow fine-tuning of electrical characteristics while keeping the overall process flow compatible with existing manufacturing capabilities.
Solution Approach 2:
The patent employs sacrificial metal-containing layers during fabrication that are selectively removed or transformed through annealing processes. These intermediate layers facilitate precise threshold voltage adjustment and are then discarded, leaving only the final optimized gate structure. This approach enables complex adjustments without permanently increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the reliability and performance of transistors by adjusting threshold voltages, improving indices such as PBTI and NBTI, and reducing leakage current, thereby addressing the limitations of existing technologies in achieving desired voltage levels.
Implementation Method 1
performing a first annealing process with respect to the first metal-containing layer
Implementation Method 2
performing a second annealing process with respect to the second metal-containing layer
Implementation Method 3
performing a first annealing process with reducing or oxidizing gases to adjust the effective work function
Data Source
AI summary
A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.