Gate-Enclosed MOSFET Switch Layout for Low-Parasitic Analog Front Ends
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Solution Overview
Problem
Conventional linear Metal Oxide Semiconductor Field Effect Transistor (MOSFET) switches in configurable analog integrated circuits exhibit parasitic capacitance and diode leakage, limiting circuit performance and configurability due to their larger source or drain area, which restricts the flexibility and efficiency of analog signal routing.
Innovation Solution
The use of non-standard device layouts for MOSFETs, specifically Substantially Gate Enclosed Field Effect Transistors (SGEFTs) with a gate that encloses the inner electrode, reduces parasitic properties by about ¼ compared to conventional linear MOSFETs, allowing for more switches on the IC and lower diode leakage currents, thereby enhancing configurability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional linear MOSFET switches are used in configurable analog circuits, then the circuit can be implemented with standard device layouts, but parasitic capacitance and diode leakage increase, limiting circuit performance and configurability
Solution Approach 1:
The patent inverts the conventional linear layout of MOSFET switches to a substantially gate enclosed configuration. Instead of having the gate linearly positioned between source and drain, the gate completely surrounds the inner electrode (source or drain), fundamentally changing the spatial arrangement to reduce parasitic effects. This inversion of the standard layout directly addresses the harmful parasitic capacitance and diode leakage by minimizing the exposed electrode area.
Solution Approach 2:
The patent implements nesting by placing the inner electrode (source or drain) completely within the enclosed gate structure. The gate acts as an outer container that surrounds the inner electrode on all sides, creating a nested configuration where one component is embedded within another. This nesting minimizes the outer perimeter of the electrode, thereby reducing parasitic capacitance to surrounding structures and minimizing diode leakage paths.
2Ease of manufacture
If conventional linear MOSFET switches are used, then device layout is simple and standard, but the source or drain area must be extended which increases parasitic properties
Solution Approach 1:
The patent inverts the conventional linear layout approach by adopting a substantially gate enclosed configuration. Instead of extending the source or drain area linearly, the design encloses the inner electrode within a gate structure that surrounds it on at least three sides (270 degrees) or completely (360 degrees for Ring-FETs). This inverted geometry reduces the outer perimeter of the electrode while maintaining switching functionality, thereby reducing parasitic properties without compromising manufacturability.
Solution Approach 2:
The patent transitions from a one-dimensional linear layout to a two-dimensional enclosed configuration. The gate wraps around the inner electrode in a planar fashion, utilizing the available layout space more efficiently. This dimensional change allows the electrode to be completely surrounded by the gate within the same footprint, minimizing the exposed electrode perimeter and reducing parasitic effects while maintaining ease of manufacture through standard fabrication processes.
3Adaptability or versatility
If more conventional MOSFET switches are placed on the IC to increase configurability, then circuit flexibility improves, but parasitic properties of each switch limit the number of switches that can be effectively integrated
Solution Approach 1:
The patent applies the inversion principle by completely reconfiguring the MOSFET layout from linear to substantially gate enclosed. This inversion reduces the parasitic capacitance of each individual switch, allowing more switches to be integrated on the IC without exceeding parasitic limits. The reduced parasitic capacitance per switch enables higher configurability while maintaining signal integrity and performance across all configurable connections.
Solution Approach 2:
The patent utilizes multiple copies of the reduced-parasitic SGEFET switches throughout the configurable analog front end circuit. Each switch is an identical copy of the optimized SGEFET design, ensuring consistent low parasitic characteristics across all switching elements. This copying approach allows systematic integration of numerous switches with uniform performance characteristics, enabling comprehensive configurability without the parasitic accumulation that would occur with conventional MOSFETs.
Data Source
AI summary
A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus.