Self-Aligned Gate Endcap Layout for Defect-Free FinFET Plug Patterning
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits leads to challenges in lithographic processes, including trade-offs between feature dimension and spacing, and the formation of metal-in-plug defects that result in shorts between intended isolated segments, due to high aspect ratios and complex plug patterning processes.
Innovation Solution
The implementation of an inverted patterning scheme using a non-conductive metal-oxide semiconductor liner that is later converted to a conductive metal oxide material, allowing for self-aligned gate endcap architectures and reducing the need for extra mask registration, thereby improving transistor layout density and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional plug patterning processes are used with high aspect ratios, then metal-in-plug defects form causing shorts between isolated segments, but the patent uses self-aligned gate endcap architectures to eliminate these defects
Solution Approach 1:
The gate endcap structure serves dual purposes: it defines the gate region and simultaneously provides the plug pattern alignment reference. The plug pattern is self-aligned to the gate endcap, eliminating the need for separate alignment processes and reducing defects caused by misalignment in conventional high aspect ratio plug patterning.
2Area of moving object
If transistor size is reduced to increase density, then lithographic process constraints increase, but the patent uses inverted patterning to reduce transistor size by 30%
Solution Approach 1:
The patent uses inverted patterning where the gate endcap is formed first as a reference structure, and subsequent plug patterns are aligned to this endcap rather than using conventional lithographic alignment. This inversion of the patterning sequence enables smaller transistor dimensions while maintaining manufacturing precision.
Solution Approach 2:
The gate endcap structure is formed in advance before the plug patterns are created. This preliminary formation of the endcap provides a stable reference for subsequent self-aligned patterning processes, enabling precise feature placement even at reduced transistor sizes.
3Length of moving object
If multi-gate transistors are scaled down, then feature dimension and spacing trade-offs increase, but the patent uses self-aligned gate endcap to improve layout density
Solution Approach 1:
The gate endcap structure serves as both the gate definition and the alignment reference for plugs and contacts. This self-service approach eliminates the need for separate alignment margins and spacing constraints that would otherwise be required in conventional processes, enabling tighter feature spacing at scaled dimensions.
Data Source
AI summary
Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.