Gate Etch Stop Layer for Non-Planar FinFET Width Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of semiconductor devices to non-planar field effect transistors (FETs) results in inadequate device performance due to a small contact area between the gate and fin structure, leading to increased overlap capacitance and gate leakage current, which is exacerbated by lateral etching during isolation structure etching.
Innovation Solution
A gate etch stop layer is introduced to prevent lateral etching during the formation of the gate, ensuring a controlled etching process that maintains a smaller gate width and reduces overlap capacitance and gate leakage current by confining the gate shape with the etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the gate is formed without an etch stop layer, then the manufacturing process is simpler, but the gate width becomes larger due to lateral etching, increasing overlap capacitance and gate leakage current
Solution Approach 1:
An etch stop layer is formed prior to gate formation to pre-establish a boundary that prevents lateral etching during subsequent processing steps. This preliminary structural preparation ensures the gate remains confined within precise dimensions throughout the manufacturing process.
Solution Approach 2:
The etch stop layer acts as an intermediary barrier between the gate material and the underlying structures. This intermediate layer selectively resists etching, mediating the interaction between etchants and the gate region to maintain precise gate width control.
2Reliability
If the contact area between gate and fin structure is increased, then device performance improves, but overlap capacitance and gate leakage current increase
Solution Approach 1:
The etch stop layer is selectively positioned at specific locations where lateral etching would occur, providing localized protection without affecting the overall gate-fin contact area. This local intervention maintains necessary electrical contact while preventing harmful lateral expansion.
Solution Approach 2:
By introducing the etch stop layer, the etching parameters are effectively changed in the gate region. The etch rate becomes zero at the etch stop layer boundary, creating a sharp parameter transition that confines the gate width while preserving contact area elsewhere.
Data Source
AI summary
A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity.