3D Gate Structure Etching with Silicon Nitride Sidewall Passivation

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Solution Overview

Problem

Existing methods of etching silicon layers in semiconductor devices face challenges in achieving precise profile control and etching selectivity, particularly in forming three-dimensional gate structures, which are crucial for reducing processing complexity and cost.

Innovation Solution

The method involves using a silicon-containing gas and a nitrogen-containing gas, free of oxygen, to form a passivation layer of silicon nitride over the etched silicon layer, with a controlled thickness profile, and employing a reactive plasma etching process to enhance etching selectivity and prevent over-etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If existing etching methods are used to form three-dimensional gate structures, then the etching process can be performed, but etching selectivity and profile control are insufficient

Engineering Contradiction:
Improveetching selectivity and profile controlVSAvoidover-etching prevention
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A passivation layer is formed on the sidewalls of the gate structure before the main etching process. This preliminary protective layer prevents over-etching and maintains profile control during subsequent etching steps, directly addressing the insufficient etching selectivity and profile control in existing methods

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a passivation layer as an intermediary substance between the etchant and the gate structure sidewalls. This intermediate layer selectively protects the sidewalls from etching, enabling precise profile control and preventing over-etching while allowing the etching process to proceed

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple fabrication steps are performed separately, then each process can be optimized, but processing complexity and time increase

Engineering Contradiction:
Improvefabrication throughputVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines the passivation layer formation and etching processes into a single integrated step. The passivation layer is formed and etching is performed in one continuous process sequence, reducing the number of separate fabrication steps while maintaining optimal control over etching selectivity and profile

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The passivation layer serves multiple functions simultaneously: it protects sidewalls from over-etching, defines the gate structure profile, and enables precise pattern transfer. This multi-functionality reduces the need for separate process steps, thereby increasing fabrication throughput without sacrificing process optimization

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the etching process by providing enhanced profile control and selectivity, reducing the risk of over-etching and maintaining a vertical sidewall profile, while potentially allowing for a one-step etching process, thus increasing fabrication efficiency.

Implementation Method 1

etching the silicon layer is implemented using an etchant and a passivant, resulting in a silicon-nitride-containing passivation layer over a sidewall of the gate structure

Methodology Applied
Scientific EffectChemical Vapor Deposition: Chemical Vapour Deposition

Implementation Method 2

patterning the silicon-containing layer removes portions of the semiconductor layer exposed by the patterned mask

Methodology Applied
Scientific EffectChemical Etching:

Data Source

PatentUS12598933B2Semiconductor devices and methods of manufacturing the same
Publication Date: 2026.04.07 TOKYO ELECTRON LTD
  • US12598933B2 patent drawing
  • US12598933B2 patent drawing
  • US12598933B2 patent drawing

AI summary

A method includes providing a semiconductor substrate and forming a fin protruding from the semiconductor substrate. The method includes forming a silicon-containing layer over the fin. The method further includes patterning the silicon-containing layer to form a gate structure over the fin, where patterning the silicon-containing layer is implemented using an etchant and a passivant that includes a silicon-containing gas and a nitrogen-containing gas.