Gate Extender Epitaxial Growth for Low Resistance FinFETs
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Solution Overview
Problem
Non-planar semiconductor devices face high extension resistance due to traditional ion implantation, which damages the crystalline structure and results in higher resistivity, especially in the extension regions below the gate, impeding re-crystallization during high temperature annealing.
Innovation Solution
The method involves forming a gate structure with a seed layer on a finned substrate, epitaxially growing a gate extender that laterally extends over the source or drain region, and conducting a low temperature diffusion process to dope the gate extender, eliminating the need for high temperature annealing and reducing device resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional ion implantation is used to dope selected regions, then the extension regions can be doped, but the crystalline structure is destroyed resulting in high extension resistance
Solution Approach 1:
The patent changes the doping method from traditional ion implantation to in-situ doped epitaxial growth, fundamentally altering the process parameters to avoid crystalline structure destruction while achieving dopant incorporation in the extension region
Solution Approach 2:
The patent replaces the mechanical bombardment of ion implantation with a chemical epitaxial growth process, substituting a physical mechanism with a chemical one to achieve doping without damaging the crystal structure
2Stability of the object's composition
If high temperature annealing is used to re-crystallize damaged regions, then crystalline structure can be restored, but non-planar devices have higher resistivity due to surface discontinuities impeding re-crystallization
Solution Approach 1:
The patent performs preliminary doping during the epitaxial growth process itself, before any annealing is required, thereby preventing crystalline damage in the first place rather than attempting to repair it later
Solution Approach 2:
The patent converts the potential harm of requiring high temperature annealing into a benefit by using low temperature processes that are compatible with non-planar structures, turning the limitation of surface discontinuities into an advantage by avoiding the need for high temperature processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces channel resistance in semiconductor devices by enabling doping of extension regions and improving electrical conductivity without the need for high temperature annealing, thereby enhancing device performance.
Implementation Method 1
epitaxially growing a gate extender from the seed layer that laterally extends over a source or drain region of the fin
Implementation Method 2
conducting a low temperature diffusion process to diffuse a dopant within the gate extender to the source or drain region of the fin
Data Source
AI summary
A method for fabricating a semiconductor device includes receiving a finned substrate comprising an isolation layer with a plurality of semiconductor fins formed thereon, forming a gate structure over a fin that comprises a gate and a seed layer disposed below the gate and immediately adjacent to the fin, and epitaxially growing a gate extender from the seed layer that laterally extends over a source or drain region of the fin. In one embodiment, a semiconductor device includes a finned substrate comprising an isolation layer with a plurality of semiconductor fins formed thereon, a gate structure formed over a fin of the plurality of fins, the gate structure comprising a gate and a seed layer disposed below the gate and immediately adjacent to the fin, and a gate extender epitaxially grown from the seed layer that laterally extends over a source or drain region of the fin.