Gate Extension Structure for Backside Clock Wiring and Grounding
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Solution Overview
Problem
Existing integrated circuit fabrication methods face challenges in providing effective backside clock wiring and substrate grounding, particularly in nanosheet transistor structures, where conventional substrate recess techniques are inadequate and lead to floating substrates.
Innovation Solution
A semiconductor structure with a gate extension for backside clock wiring and substrate grounding is implemented, utilizing a front via backside power rail approach without extensive substrate recess, grounding the substrate at a distance from the transistor and connecting to a backside clock signal wire, thereby avoiding floating substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional substrate recess techniques are used for backside clock wiring, then wiring access is improved, but substrate grounding reliability deteriorates leading to floating substrates
Solution Approach 1:
The gate structure extends from the front surface into the substrate, creating a three-dimensional configuration where the gate extension protrudes into the substrate recess region. This dimensional extension allows the gate to serve dual purposes: providing front surface transistor control and enabling backside wiring access through the substrate, thereby resolving the contradiction between wiring accessibility and substrate grounding integrity.
Solution Approach 2:
The gate extension structure performs multiple functions simultaneously: it controls the transistor channel from the front surface, provides a conductive path for backside clock wiring, and maintains substrate grounding by remaining connected to the substrate. This multi-functionality eliminates the need for separate substrate grounding structures, preventing floating substrate issues while enabling backside wiring.
2Ease of operation
If extensive substrate recess is performed, then backside wiring access is improved, but substrate integrity deteriorates
Solution Approach 1:
Instead of creating extensive lateral substrate recesses that compromise substrate integrity, the gate structure extends vertically into the substrate. This vertical dimension approach provides wiring access pathways without removing large portions of the substrate, thereby maintaining substrate mechanical strength and integrity while still enabling backside clock wiring connectivity.
3Adaptability or versatility
If gate extension is implemented, then backside clock wiring is enabled, but device complexity increases
Solution Approach 1:
The gate extension is designed to perform multiple functions within a single structure: it provides transistor channel control from the front surface, creates conductive pathways for backside clock wiring, and maintains substrate grounding. By consolidating these functions into one structure rather than adding separate components, the actual device complexity is reduced despite the enhanced functionality.
Solution Approach 2:
The invention merges the gate control function with the wiring access function and substrate grounding function into a single integrated gate extension structure. This consolidation eliminates the need for separate substrate contacts and wiring structures, thereby reducing overall device complexity while achieving backside clock wiring capability.
Data Source
AI summary
Embodiments of the present disclosure include a semiconductor structure having a transistor including epitaxial regions and a gate structure at a frontside, a gate extension being connected at the frontside to the gate structure and extending to a backside, the frontside being opposite the backside. A backside gate contact is connected at the backside to the gate extension. A source/drain via is coupled to one of the epitaxial regions, the source/drain via extending through the gate structure from the frontside to the backside, the gate extension extending further in the backside than the source/drain via.