Gate Extension Segmentation for Backside Power Rail Routing
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Solution Overview
Problem
The existing methods for connecting gate contacts to backside power rails in semiconductor devices are challenging, especially in decreasing node sizes, due to limited placement options and difficulty in maintaining electrical integrity.
Innovation Solution
The solution involves forming a gate extension within the region between two transistors of opposite conductivity, cutting the gate extension into portions using a gate cut, and connecting each portion to a backside power rail via local interconnects, thereby facilitating efficient wire routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate contacts are placed in N2N or P2P spaces under adjacent transistors, then power distribution is simplified, but gate contact placement options are limited and routing becomes difficult
Solution Approach 1:
The patent extends the gate contact into the third dimension by creating a vertical gate extension through the substrate, allowing the gate to reach the backside of the device. This dimensional transition enables gate contacts to be placed in constrained front-side regions while maintaining routing flexibility at the backside, resolving the contradiction between limited placement options and routing difficulty.
Solution Approach 2:
The gate structure is segmented into multiple portions along its length, with different sections serving different functions: the front-side portion connects to the gate electrode, the intermediate portion extends through the substrate, and the backside portion connects to power rails. This segmentation allows each portion to be optimized independently for its specific function.
2Productivity
If node sizes are decreased to increase transistor density, then device integration is improved, but maintaining electrical integrity of conductive components becomes more difficult
Solution Approach 1:
The patent applies different material properties and structural characteristics to different portions of the gate structure. The gate extension portions are designed with specific width variations, and different regions use different filling materials (conductive material vs. dielectric material) to optimize local electrical characteristics. This local quality approach maintains electrical integrity even as overall dimensions are reduced.
Solution Approach 2:
The patent changes geometric parameters of the gate extension, particularly the width of different portions, to control electrical properties. By adjusting the width of gate extension portions and using selective filling, the invention maintains appropriate resistance and capacitance values even when node sizes are decreased, thereby preserving electrical integrity at higher densities.
3Reliability
If gate extension is made continuous to maintain electrical connection, then conductivity is improved, but electrical isolation between adjacent gates becomes difficult
Solution Approach 1:
The patent extracts or removes conductive material from specific regions of the gate extension where adjacent gates would otherwise be electrically connected. By creating gaps or filling certain portions with dielectric material, the invention maintains continuity within each gate structure while providing necessary isolation between adjacent gates, thus resolving the contradiction between conductivity and isolation.
Data Source
AI summary
A semiconductor device includes a gate metal and a gate extension disposed within a region between two transistors of opposite conductivity and connected to the gate metal. The gate extension extends toward a side of the semiconductor device having power rails. A gate cut is disposed within the gate metal and through the gate extension to cut the gate extension into portions that are electrically isolated from each other. Each of the portions of the gate extension is coupled to a backside power rail.