High-Voltage Gate Field Plate Layout for Lower On-Resistance
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Solution Overview
Problem
Conventional high voltage semiconductor devices face issues with deteriorated on-resistance (Rsp) characteristics due to longer current paths caused by the STI region and inefficient etching processes that form field plates and insulating patterns with different widths, leading to decreased process efficiency and HE-SOA characteristics.
Innovation Solution
The proposed solution involves forming a thin film-shaped gate field plate below the gate region to mitigate electric field concentration and using a single mask pattern to form the field plate and insulating pattern together, ensuring the gate field plate has a thickness less than half that of the gate region, and incorporating a lower well region to expand the depletion region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an STI region is formed from the surface to a deep position within the substrate to prevent electric field concentration, then HE-SOA characteristics are improved, but the current path becomes longer and on-resistance deteriorates
Solution Approach 1:
The gate field plate is positioned below the gate region at a different depth dimension, extending from the surface toward the drift region but stopping before reaching the STI region. This spatial arrangement allows the gate field plate to mitigate electric field concentration at the gate edge without forcing current to travel along the bottom of the deep STI region, thus resolving the contradiction between improving HE-SOA characteristics and maintaining short current path length
Solution Approach 2:
The gate field plate is designed with specific local properties: it is positioned only below the gate region rather than across the entire device, and its thickness is controlled to be less than half that of the gate region. This localized structure provides electric field mitigation exactly where needed at the gate edge while minimizing interference with the overall current flow path through the drift region
2Manufacturing precision
If separate etching processes are used to form field plate and insulating pattern with different widths, then manufacturing precision is improved, but process efficiency decreases
Solution Approach 1:
The field plate and insulating pattern are formed in a single etching process using one mask pattern. The mask pattern is designed with different width regions that simultaneously define both the field plate width and the insulating pattern width. This merging of formation steps into one process achieves both structures with precise width control while eliminating the need for separate etching processes, thus resolving the contradiction between manufacturing precision and process efficiency
Data Source
AI summary
Proposed are a high voltage semiconductor device and a method of manufacturing the same and, more particularly, a high voltage semiconductor device and a method of manufacturing the same seeking to improve on-resistance (Rsp) characteristics of the device by forming a field plate on a substrate and above a gate region, and prevent deterioration of HE-SOA characteristics by forming a thin film-shaped gate field plate below the gate region to mitigate an electric field concentrated below the field plate and on an edge of the gate region.