Simultaneous Gate and Field Electrode Trench Formation
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Solution Overview
Problem
Current methods for forming needle-trench configured power semiconductor devices are complex and time-consuming due to the need for multiple processing steps, which increases fabrication time and expense.
Innovation Solution
A method is developed to simultaneously form upper and gate trenches using a single mask, allowing for the use of a protective layer that simplifies lithography steps and reduces misalignment issues, while enabling deeper and wider field electrode trenches without altering the gate trench, thus reducing processing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple processing steps are used to form needle trenches, then manufacturing precision can be maintained, but device complexity and fabrication time increase
Solution Approach 1:
The patent combines the formation of gate trenches and field electrode trenches into a single simultaneous etching process using one mask layer, merging two separate processing steps into one. This reduces device complexity and fabrication time while maintaining the precision needed for properly positioned trenches through a single aligned patterning operation.
Solution Approach 2:
The single mask layer serves multiple functions: it defines both the gate trench pattern and the field electrode trench pattern simultaneously. This universal patterning approach eliminates the need for separate masks for each trench type, reducing processing complexity while maintaining manufacturing precision through unified alignment.
2Manufacturing precision
If multiple processing steps are used to form needle trenches, then trench formation accuracy can be achieved, but loss of time increases
Solution Approach 1:
The patent merges the formation of gate trenches and field electrode trenches into a single simultaneous etching process, reducing fabrication time by eliminating sequential processing steps while maintaining trench formation accuracy through unified patterning in one aligned operation.
3Productivity
If conventional trench formation methods are used, then processing can be completed, but misalignment issues occur
Solution Approach 1:
The patent combines gate trench and field electrode trench formation into a single etching process using one mask, ensuring perfect alignment between the two trench types. This unified approach eliminates misalignment issues that occur with conventional sequential methods while maintaining processing efficiency.
Solution Approach 2:
The mask layer is designed in advance to define both gate and field electrode trench patterns simultaneously, establishing precise alignment relationships before the etching process begins. This preliminary patterning action prevents misalignment issues during subsequent processing steps.
Data Source
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AI summary
An upper portion of a field electrode trench and a gate trench are simultaneously formed in the main surface of a substrate to approximately the same depth. A first protective layer is formed that completely fills the gate trench and lines the upper field electrode trench. The first protective layer is removed from the bottom of the upper trench and semiconductor material is removed thereby forming a lower portion of the field electrode trench while the gate trench remains completely filled by the first protective layer. An electrically conductive field electrode and a field electrode dielectric are formed in the field electrode trench. At least some of the first protective layer is removed from the gate trench. A conformal gate dielectric layer is formed on the substrate. An electrically conductive gate electrode is formed in the gate trench while the field electrode remains covered by the gate dielectric layer.