Gate Fill Using Replacement Spacer for Nanosheet MOSFETs
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Solution Overview
Problem
As semiconductor devices like nanosheet MOSFETs are scaled down, challenges arise in filling low resistance materials such as tungsten in the gate region to reduce gate resistance, especially at contacted poly pitch (CPP) scaling beyond 7 nanometers, due to limited space and high resistance of work function metals used.
Innovation Solution
The technique involves forming outer spacers surrounding a dummy gate over a channel stack, removing the dummy gate and spacers, and performing a channel release to deposit a dielectric layer and work function metal, followed by filling the gate with a low resistance metal like tungsten using a replacement spacer method, which reduces gate resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If work function metal is used in the gate region, then the gate structure is formed, but the gate resistance is high
Solution Approach 1:
The gate structure is divided into multiple segments: work function metal layers (first and second) and a low resistance metal layer filled between them. This segmentation allows each layer to perform its specific function - the work function metals provide the necessary work function for the transistor, while the low resistance metal reduces gate resistance without interfering with the work function requirement.
Solution Approach 2:
The low resistance metal layer is nested between the work function metal layers within the gate structure. This nested configuration allows the low resistance metal to be embedded in the gate region without removing the work function metals, thereby reducing gate resistance while maintaining the gate structure's electrical characteristics.
2Reliability
If low resistance metal is filled in the gate region, then gate resistance is reduced, but the gate structure becomes more complex
Solution Approach 1:
The first work function metal layer is deposited before filling the low resistance metal, and the second work function metal layer is deposited after filling. This preliminary and sequential action ensures that the low resistance metal is properly enclosed by the work function metals, reducing gate resistance while maintaining a manageable manufacturing process through controlled sequencing.
Solution Approach 2:
The low resistance metal acts as an intermediary layer between the source and drain regions through the gate, providing a low resistance path for gate current. This intermediary layer reduces gate resistance without requiring fundamental changes to the overall gate structure design.
3Length of moving object
If gate dimensions are scaled down, then device size is reduced, but filling low resistance material becomes difficult
Solution Approach 1:
The low resistance metal is filled in the vertical dimension between the work function metal layers rather than only in the lateral dimension. This vertical filling approach allows effective reduction of gate resistance even as lateral gate dimensions are scaled down, overcoming the limitations of conventional lateral filling methods.
Solution Approach 2:
The manufacturing process parameters are changed to accommodate scaled dimensions: the thickness of the low resistance metal layer and the spacing between work function metal layers are adjusted to maintain effective gate resistance reduction at smaller scales. This parameter optimization ensures the solution remains effective as device dimensions are reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate resistance by filling low resistance metals in the gate region, enhancing the operational characteristics of nanosheet MOSFETs by improving switching speeds and reducing the aspect ratio of the gate, thereby addressing the limitations of high resistance work function metals.
Implementation Method 1
performing conformal deposition of a dielectric layer and a work function metal on exposed portions of the oxide
Data Source
AI summary
A semiconductor structure includes a substrate and a channel stack disposed over a portion of a top surface of the substrate, the channel stack including two or more nanosheet channels, inner spacers disposed above and below outer edges of the two or more nanosheet channels, work function metal disposed between the inner spacers above and below each of the two or more nanosheet channels, and a dielectric layer disposed between the work function metal and the inner spacers and two or more nanosheet channels. The semiconductor structure further includes source/drain regions disposed over the top surface of the substrate surrounding the channel stack and a gate region disposed over a top surface of the channel stack, the gate region including the work function metal and a gate metal disposed over the work function metal. The semiconductor structure further includes a capping layer and contacts.