Semiconductor Cell Layout Using Gate-Fin Overlap to Reduce Height
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Solution Overview
Problem
Existing design rules for semiconductor devices result in wasted space due to restrictions on gate patterns not overlapping straddling fin patterns, leading to reduced cell density and inefficient use of layout area.
Innovation Solution
Allowing gate patterns to overlap and electrically couple with straddling fin patterns, enabling a ⅖ reduction in height of semiconductor cells, thereby improving cell and layout density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate patterns are restricted from overlapping straddling fin patterns, then manufacturing reliability is improved, but cell density deteriorates
Solution Approach 1:
The patent inverts the conventional approach by allowing gate patterns to overlap straddling fin patterns, reversing the traditional restriction. This inversion enables the cell to utilize the straddling fin pattern effectively, reducing cell height from 5TP to 3TP while maintaining manufacturing reliability through careful electrical coupling design.
Solution Approach 2:
The patent changes the dimensional relationship between gate patterns and fin patterns by allowing overlap in the vertical dimension. Instead of maintaining strict separation, the gate pattern is positioned to overlap the straddling fin pattern, utilizing the vertical space more efficiently to reduce overall cell height.
2Quantity of substance
If gate patterns overlap straddling fin patterns, then cell density is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent applies local quality by creating different electrical coupling conditions in different regions of the cell. The gate pattern is electrically coupled to the straddling fin pattern in the overlap region, while other regions maintain traditional isolation. This localized electrical coupling enables density improvement without compromising overall manufacturing precision.
3Area of stationary object
If cell height is reduced, then layout efficiency is improved, but design rule complexity worsens
Solution Approach 1:
The patent changes the critical parameter of cell height from 5TP to 3TP by modifying the overlap relationship between gate and fin patterns. This parameter change is achieved through updated design rules that permit and define the specific overlap geometry, enabling more efficient layout while managing complexity through standardized overlap specifications.
Data Source
AI summary
A semiconductor device includes: first (F-fin) and second (S-fin) conductivity type fins, a first row including an alpha-type (α-type) and a beta-type (β-type) cell region having a single-row height; the α-type cell region including a first F-fin, a first S-fin, and a first gate structure; top and bottom edges of the α-type cell region being aligned with top and bottom boundaries of the first row and free from overlap by the first F-fin or first S-fin; the first gate structure overlapping the first F-fin and first S-fin, and free from overlapping top and bottom edges of the α-type cell region; the β-type cell region including a second F-fin, a second S-fin, a third F-fin, a third S-fin, and a second gate structure; the second gate structure overlapping the second and third F-fins and second and third S-fins, and overlapping at least one of the third F-fin or the third S-fin.