Gate Finger Elements Over Isolation Regions for High Voltage Transistors
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Solution Overview
Problem
The downscaling of high voltage transistors is limited by the need for large contact-to-gate spacing to maintain high drain-source breakdown voltage and supply drive current, resulting in wide devices with high on-resistance, which hinders the miniaturization of semiconductor memory devices.
Innovation Solution
The implementation of a semiconductor device with a reduced surface field (RESURF) effect, where gate finger elements are formed over isolation regions to enhance depletion and evenly distribute the electrical field, increasing breakdown voltage without increasing device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If contact-to-gate spacing is increased to maintain high drain-source breakdown voltage, then breakdown voltage is improved, but device size increases
Solution Approach 1:
The patent extends the gate structure vertically by forming gate fingers that overlap with isolation regions in the vertical dimension. This dimensional extension allows the gate to exert control over drain extensions without requiring increased horizontal spacing, thereby maintaining breakdown voltage while reducing device footprint.
Solution Approach 2:
The gate is divided into multiple gate fingers that are distributed across the device structure. These segmented gate fingers individually control different drain extension regions, providing comprehensive control while allowing compact horizontal arrangement that reduces overall device size.
2Power
If device width is increased to supply drive current, then drive current capability is improved, but on-resistance increases
Solution Approach 1:
The patent applies different gate finger configurations to different local regions. Drain extensions underlying gate fingers receive enhanced control and depletion, while other regions maintain standard characteristics. This localized approach allows drive current to be increased through parallel conduction paths without proportionally increasing on-resistance.
3Reliability
If gate fingers are formed over isolation regions, then electrical field distribution is improved, but manufacturing complexity increases
Solution Approach 1:
The patent combines the gate formation process with the existing isolation region structure. Gate fingers are formed to overlap with isolation regions that are already present from previous fabrication steps, merging two functions (isolation and gate control) into a unified structure that achieves improved field distribution without adding separate manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher breakdown voltage while reducing device size, optimizing the BVdss-Ron ratio and enabling more compact semiconductor memory devices.
Implementation Method 1
The poly gate fingers 51 induce a capacitive coupling with the STI regions 40, which enhances the depletion of the drain extensions 33
Implementation Method 2
enhances the depletion of the drain extensions 33. As a result, the electrical field is more evenly distributed over the drain extensions 33, thus inducing a higher breakdown voltage (BVdss)
Data Source
AI summary
Embodiments of the present invention describe a semiconductor device implementing the reduced-surface-field (RESURF) effect. The semiconductor device comprises a source/drain region having a plurality of isolation regions interleaved with source/drain extension regions. A gate electrode is formed on the semiconductor device, where the gate electrode includes gate finger elements formed over the isolation regions to induce capacitive coupling. The gate finger elements enhance the depletion of the source/drain extension regions, thus inducing a higher breakdown voltage.