Replacement Gate Structure With Fluorine Diffusion for Leakage Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into a given chip area, including issues with charge buildup in gate dielectric layers that can lead to leakage paths and reliability problems in transistors.
Innovation Solution
A method is introduced to selectively incorporate fluorine into gate dielectric layers of replacement gate stacks, combined with dipole dopant species to tune work functions and threshold voltages, which involves forming fluorine-containing layers, annealing to diffuse fluorine, and removing protection layers to reduce charge buildup and enhance transistor reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fluorine is incorporated into gate dielectric layers to reduce charge buildup and improve reliability, then transistor reliability is improved, but the manufacturing process complexity increases due to additional fluorine-containing layer formation and annealing steps
Solution Approach 1:
A fluorine-containing layer is formed on the gate dielectric layer before final transistor completion. This preliminary fluorine incorporation reduces charge buildup in the gate dielectric, improving transistor reliability. The fluorine-containing layer is subsequently removed after serving its protective and functional purpose, demonstrating preliminary action where a layer is added temporarily to achieve a specific effect during manufacturing.
Solution Approach 2:
The fluorine-containing layer acts as an intermediary substance that facilitates fluorine diffusion into the gate dielectric layer during annealing. This intermediary layer enables controlled fluorine incorporation to reduce charge buildup without requiring direct fluorine gas exposure or complex ion implantation equipment, thus improving reliability while managing process complexity.
2Productivity
If feature size is reduced to integrate more components into a given chip area, then integration density is improved, but charge buildup in gate dielectric layers increases leading to leakage paths
Solution Approach 1:
The fluorine-containing layer is selectively formed only on gate dielectric layers in regions where transistors are to be formed, providing localized fluorine incorporation. This local quality approach addresses charge buildup specifically in the gate dielectric without affecting other device regions, enabling higher integration density while maintaining transistor reliability through targeted fluorine diffusion to reduce charge accumulation.
Solution Approach 2:
Fluorine incorporation changes the physical and chemical parameters of the gate dielectric layer, including its electrical properties. The fluorine atoms modify the dielectric's charge trapping characteristics, reducing charge buildup and preventing leakage paths. This parameter change allows smaller feature sizes to be used without sacrificing transistor reliability, thereby improving integration density.
3Reliability
If fluorine-containing layer is formed on gate dielectric layer to diffuse fluorine, then charge buildup is reduced, but the manufacturing steps and time increase
Solution Approach 1:
The formation of the fluorine-containing layer is merged with existing manufacturing processes. The fluorine-containing layer can be deposited using standard CVD or ALD equipment already present in the fabrication line, and the subsequent annealing step is combined with other thermal processing steps in the manufacturing flow. This merging approach reduces fluorine diffusion time and manufacturing cycle time while maintaining transistor reliability improvements.
Solution Approach 2:
The fluorine-containing layer is formed as a preliminary step that prepares the gate dielectric for subsequent processing. By incorporating fluorine early in the manufacturing sequence, the layer serves multiple purposes: it protects the gate dielectric during processing and provides the fluorine source for charge reduction. This preliminary action optimizes the timing of fluorine incorporation, reducing overall manufacturing cycle time while achieving reliability improvements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the tuning of threshold voltages without affecting gate spacings, reducing leakage paths and improving the reliability of transistors by localizing electrons and bonding with dipole dopants, enabling smaller transistor sizes and improved performance.
Implementation Method 1
annealing to diffuse fluorine
Implementation Method 2
annealing to diffuse fluorine
Implementation Method 3
bonding with dipole dopants
Data Source
AI summary
A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.