Gate Fringe Area Reduction in High Voltage FETs
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Solution Overview
Problem
High voltage field effect transistors often suffer from surface breakdown voltage due to complex extended low doped drain (LDD) structures, which increase process complexity and cost.
Innovation Solution
The implementation of a semiconductor structure with shallow trench isolation and dielectric gate spacers that surround field effect transistors, featuring a gate electrode with four sides and offset spacers on two sides, which reduces the gate fringe area and prevents leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex extended low doped drain (LDD) structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the complex extended LDD structure from the device design. Instead of using the traditional complex LDD approach, the invention uses a simplified structure with dielectric gate spacers and shallow trench isolation that achieves the same surface breakdown protection without the additional process complexity
Solution Approach 2:
The dielectric gate spacers serve multiple functions simultaneously: they provide surface breakdown protection, define the gate fringe area, and work with the shallow trench isolation to prevent collateral dopant implantation. This multi-functionality replaces the need for separate complex LDD structures
2Reliability
If complex extended low doped drain (LDD) structures are used to improve surface breakdown characteristics, then surface breakdown voltage is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the expensive complex extended LDD structure and replaces it with a more manufacturable approach using dielectric gate spacers and shallow trench isolation, reducing manufacturing cost while maintaining surface breakdown protection
Solution Approach 2:
The invention uses standard dielectric materials and shallow trench isolation processes that are already part of conventional manufacturing workflows, replacing the need for expensive and complex extended LDD processing steps
3Reliability
If gate fringe area is reduced by using dielectric gate spacers and shallow trench isolation, then surface breakdown characteristics are enhanced, but gate electrode structure becomes more complex
Solution Approach 1:
The patent introduces asymmetry in the gate electrode structure by adding dielectric gate spacers only on specific sides (two sides with offset spacers, two sides contacted directly). This asymmetric configuration precisely controls the gate fringe area to minimize surface breakdown while maintaining manufacturing feasibility
Solution Approach 2:
The gate electrode structure is segmented into different regions with different spacer configurations: two sides have dielectric offset spacers providing indirect contact, while the other two sides have direct dielectric gate spacer contact. This segmentation allows precise control of the gate fringe area
4Object-generated harmful factors
If dielectric gate spacers are configured to minimize gate fringe area, then leakage current is prevented, but manufacturing precision requirements increase
Solution Approach 1:
The dielectric gate spacers are formed preliminarily before the gate electrode, establishing the precise boundaries and minimizing the gate fringe area in advance. This preliminary action prevents leakage current paths from forming and reduces the precision requirements for subsequent processing steps
Solution Approach 2:
The dielectric gate spacers act as intermediary structures that precisely define the boundary between the gate electrode and the active region. This intermediary layer controls the gate fringe area and prevents direct contact that would create leakage paths, while being compatible with standard manufacturing processes
Data Source
AI summary
A semiconductor structure includes at least two field effect transistors. A gate strip including a plurality of gate dielectrics and a gate electrode strip can be formed over a plurality of semiconductor active regions. Source/drain implantation is conducted using the gate strip as a mask. The gate strip is divided into gate electrodes after the implantation.