Gate-Fusion Transpilation Caching for Quantum Circuit Simulation

The patent pre-computes and stores gate-fusion transpilation procedures in a cache before they are needed. When a quantum circuit requires gate fusion, the system checks the cache for an existing procedure matching the circuit configuration, retrieves it if available, or creates and stores it for future use. This preliminary action eliminates the need to perform computationally expensive gate fusion analysis at simulation time, resolving the contradiction between reducing memory footprint through gate fusion and avoiding the computational cost of gate fusion time.

The patent creates a cached copy of the gate-fusion transpilation procedure after the first execution. Instead of re-computing the optimization procedure for each quantum circuit with the same configuration, the system copies the pre-computed procedure from cache and reuses it. This copying approach maintains circuit optimization quality while dramatically reducing transpilation execution time for subsequent circuits.

The patent segments the transpilation process into distinct phases: cache lookup phase and gate fusion execution phase. The cache lookup checks whether a pre-computed procedure exists for the given circuit configuration, separating the complex gate fusion computation from the routine simulation workflow. This segmentation allows the system to achieve simulation efficiency improvements through gate fusion while managing transpilation complexity by handling it only when necessary (cache miss) rather than for every circuit.