Gate Electrode Grain Size Control for CMP Height Uniformity
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Solution Overview
Problem
The CMP process in semiconductor manufacturing induces gate height variations due to differing polishing rates in regions of varying pattern density, leading to device mismatch and non-uniformity.
Innovation Solution
Selective doping of the metal layer in regions with smaller metal grain size to control polishing rates, reducing the CMP loading effect and achieving uniform gate heights across the IC chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If CMP process is used to planarize metal layers, then surface flatness is improved, but gate height uniformity deteriorates due to varying polishing rates in different pattern density regions
Solution Approach 1:
The patent applies local quality by selectively doping metal grains in specific regions (e.g., regions with larger metal grain sizes) to alter their polishing characteristics. This creates spatially varying material properties where doped regions polish at different rates than undoped regions, compensating for pattern density variations and achieving uniform gate heights across the wafer while maintaining surface flatness
2Speed
If metal grain size is reduced through doping, then polishing rate is increased, but metal layer homogeneity deteriorates
Solution Approach 1:
The patent selectively dopes metal grains only in specific regions rather than uniformly across the entire metal layer. This localized approach allows polishing rate enhancement in targeted areas while preserving the natural metal grain structure and composition in other regions, thereby maintaining overall metal layer homogeneity while achieving the desired polishing rate variation
Solution Approach 2:
The patent changes the chemical composition parameter of the metal layer by introducing dopants to specific regions. This parameter change alters the physical properties (polishing rate) of the doped regions without fundamentally changing the metal layer structure, enabling controlled variation in polishing behavior while maintaining compositional stability in undoped regions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances gate height uniformity and improves device performance by controlling metal polishing rates in areas of different pattern densities.
Implementation Method 1
dopants are implanted into a portion of the gate electrode layer in the second region of the substrate, reducing a grain size of metal in the doped metal portion
Implementation Method 2
excess portions of the gate electrode layer are removed to form the gate electrode in each of the gate cavities
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.