Shallow Trench Isolation Gate Groove for Leakage Reduction
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Solution Overview
Problem
As transistor pitch decreases in semiconductor devices, reliability against Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI) is compromised due to increased electric field intensity and Gate-Induced-Drain-Leakage current, while reducing voltage to mitigate these issues decreases transistor performance and increases leakage current, making it difficult to achieve both performance and reliability.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with regions of different conductivity types, isolation regions, and transistors with gate electrodes buried in shallower grooves, sharing a cap insulating film to reduce leakage current and maintain transistor performance, allowing for a lower power consumption design and improved reliability against HCI.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the pitch of transistors is decreased to improve transistor performance, then the transistor performance is improved, but the reliability against HCI and BTI deteriorates due to increased electric field intensity
Solution Approach 1:
The gate structure is segmented into two distinct parts: a first gate electrode extending over the active region and a second gate electrode extending over the isolation region. This segmentation allows independent optimization of each gate's function - the first gate controls transistor performance while the second gate manages electric field distribution to reduce HCI and BTI effects, thereby resolving the contradiction between performance and reliability.
Solution Approach 2:
A third gate electrode is introduced as an intermediary element positioned between the first and second gate electrodes. This intermediate gate serves as a buffer that further modulates the electric field distribution in the channel region, providing additional control over carrier injection and reducing the harmful effects of high electric fields while maintaining transistor performance.
2Reliability
If the voltage Vpp is set low to reduce GIDL and abnormal contact leakage, then the leakage current is reduced, but the transistor performance in the memory cell decreases
Solution Approach 1:
Different regions of the gate structure are assigned different electrical characteristics through the multi-gate configuration. The first gate electrode operates at higher voltage to maintain strong inversion and high transistor performance, while the second gate electrode operates at lower voltage to reduce GIDL and abnormal contact leakage. This local differentiation of electrical properties allows simultaneous optimization of both performance and leakage reduction.
3Productivity
If the pitch of transistors is decreased, then the transistor density is increased, but abnormal contact leakage occurs more frequently due to smaller margin in contact with gate electrode
Solution Approach 1:
The gate structure transitions from a single-planar gate to a three-dimensional multi-layer gate configuration with electrodes at different vertical levels. This dimensional change allows the gate electrodes to overlap in the vertical dimension while maintaining horizontal spacing, thereby increasing transistor density without compromising the margin for abnormal contact leakage. The overlapping gates provide both high density and reliable electrical isolation.
Data Source
AI summary
Semiconductor devices have a substrate including first and second regions of differing conductivity types and a shallow trench isolation isolation region that extends within the first and second regions. First and second active regions are disposed in respective first and second regions, with a gate electrode disposed in a lower portion of a gate groove that extends continuously from the first active region to the second active region, the gate groove being shallower than the shallow trench. A cap insulating film is disposed in an upper portion of the gate groove covering an upper surface of the gate electrode. First and second transistors are within respective first and second active regions and share the gate electrode.