Gate Height Variation for Threshold Voltage Control in Multi-Gate Transistors
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Solution Overview
Problem
Existing multi-gate transistor fabrication processes, such as those for FinFETs and MBC transistors, face challenges in achieving precise control over threshold voltages due to the consumption of threshold-voltage-determining species like aluminum during gate recess processes, which affects n-type and p-type transistors differently.
Innovation Solution
The proposed solution involves differential gate recessing techniques and the use of a selective metal layer to modulate threshold voltages, where the gate structures are recessed to varying depths and a selective metal layer is deposited to adjust the threshold voltage levels, allowing for the fabrication of transistors with distinct threshold voltages by controlling the consumption of work function layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate recess process is performed to make room for dielectric cap layer, then self-aligned contact formation is enabled, but threshold-voltage-determining species like aluminum are consumed affecting threshold voltage control
Solution Approach 1:
The patent applies different recess depths to different gate structures (first gate structure vs. second gate structure) to achieve different threshold voltages. The first gate structure is recessed to a first depth while the second gate structure is recessed to a second depth, creating local variations in gate height that determine threshold voltage. This local differentiation resolves the contradiction by enabling both the necessary recess for contact formation and precise threshold voltage control through selective depth variation.
2Adaptability or versatility
If gate structures are recessed to varying depths, then different threshold voltages are achieved, but process complexity increases
Solution Approach 1:
The patent uses a dummy gate structure formed in advance that serves as a template for the final gate structures. The dummy gate is formed with specific dimensions and positioned precisely, then used as a reference for subsequent recess operations. This preliminary action simplifies the overall process by establishing a known reference point before the complex differential recessing operations, reducing the need for multiple measurement and adjustment steps.
Solution Approach 2:
The dummy gate structure acts as an intermediary element that facilitates the formation of the final gate structures with different heights. The dummy gate is formed first, then gate spacers are deposited on its sidewalls, and finally the dummy gate is removed and replaced with metal gate material. This intermediary structure enables precise positioning and height control of the final gates without requiring direct complex patterning of each gate to different heights.
3Reliability
If metal gate structure is recessed, then dielectric cap layer can be deposited for protection, but work function layers are consumed
Solution Approach 1:
The patent deposits the dielectric cap layer selectively on the recessed portions of the gate structures. The cap layer fills the recesses created during the gate recess process, protecting the metal gate and work function layers in those specific areas where recess occurred. This local protection approach ensures that the cap layer is present only where needed for protection during self-aligned contact formation, minimizing unnecessary material consumption while maintaining reliability.
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A semiconductor structure includes a substrate, a first active region, a second active region and a third active region over the substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, a third gate structure over a channel region of the third active region, a first cap layer over the first gate structure, a second cap layer over the second gate structure, and a third cap layer over the third gate structure. A height of the second gate structure is smaller than a height of the first gate structure or a height of the third gate structure.