Gate Height Variation for Multi-Transistor Threshold Voltage Tuning
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Solution Overview
Problem
Existing multi-gate transistor fabrication processes, such as those for FinFETs and MBC transistors, face challenges in achieving consistent and differentiated threshold voltages due to the consumption of threshold-voltage-determining species like aluminum during gate recess processes, which affects n-type and p-type transistors differently.
Innovation Solution
The method involves selectively recessing and globally recessing gate structures with varying etch rates and applying a selective metal layer to modulate threshold voltages, ensuring distinct threshold voltages for different transistor types by controlling the consumption of work function layers and gate heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate recess process is applied to fabricate multi-gate transistors, then gate structure is formed with proper depth, but threshold-voltage-determining species like aluminum are consumed affecting transistor performance
Solution Approach 1:
The patent applies different recess depths to different gate structures based on their specific requirements. First gate structures receive a first recess depth while second gate structures receive a second recess depth, creating local variations in gate height to achieve different threshold voltages for n-type and p-type transistors respectively, thereby resolving the contradiction between uniform manufacturing and differentiated performance requirements
Solution Approach 2:
The patent modifies the recess depth parameter selectively across different gate structures. By controlling the recess depth as a variable parameter rather than applying a uniform value, the process achieves both proper gate structure formation and differentiation of threshold voltages, transforming a single-parameter process into a multi-parameter control system that resolves the contradiction
2Manufacturing precision
If selective metal layer is added to manage gate resistance, then threshold voltage modulation is improved, but device structure becomes more complex
Solution Approach 1:
The selective metal layer is deposited over the recessed gate structures before subsequent processing steps. This preliminary action allows the metal layer to be positioned precisely where needed to modulate threshold voltages and manage gate resistance, and the structure is built up in a controlled sequence that minimizes overall complexity
Solution Approach 2:
The selective metal layer serves as an intermediary element between the gate structure and the surrounding dielectric materials. It performs dual functions of threshold voltage modulation and gate resistance management, acting as a mediating layer that achieves multiple objectives without requiring separate structures for each function
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A semiconductor structure includes a substrate, a first active region, a second active region and a third active region over the substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, a third gate structure over a channel region of the third active region, a first cap layer over the first gate structure, a second cap layer over the second gate structure, and a third cap layer over the third gate structure. A height of the second gate structure is smaller than a height of the first gate structure or a height of the third gate structure.